PSoC 6 WiFi-BT Pioneer Kit Guide, Doc. # 002-22677 Rev. *B
38
4.
Kit Hardware
4.1
CY8CKIT-062-WiFi-BT Details
The PSoC 6 WiFi-BT Pioneer Kit is built around the PSoC 6 MCU;
shows the block
diagram of the device. For details of the PSoC 6 MCU features, see the
Figure 4-1. PSoC 6 MCU Block Diagram
CPU Subsystem
System Interconnect (Multi Layer AHB , MPU/SMPU, IPC)
ROM
128 KB
ROM Controller
CRYPTO
DES/TDES,
AES,SHA,CRC,
TRNG,RSA/ECC
Accelerator
Initiator/MMIO
SWJ/MTB/CTI
8KB Cache
Cortex M0+
100 MHz (1.1V)
25 MHz (0.9V)
MUL, NVIC, MPU
IO Subsystem
Peripheral Interconnect (MMIO, PPU)
IO
S
S
G
P
IO
PCLK
104 GPIOs (6 of these are OVT Pins)
EFU
SE
(1
0
24
b
its
)
PSoC 62
S
eri
al
M
em
or
y I/F
(Q
S
P
I w
ith
O
T
F
E
nc
ry
p
tio
n
/D
ec
ry
pt
io
n
))
DMA
MMIO
USB-
F
S
H
os
t +
D
ev
ic
e
FS
/L
S
PH
Y
FLASH
1024+32 KB
FLASH Controller
SWJ/ETM/ITM/CTI
FPU, NVIC, MPU, BB
Cortex M4
150 MHz (1.1V)
50 MHz (0.9V)
8KB Cache
SRAM
9x 32 KB
SRAM Controller
E
ne
rg
y P
ro
file
r
x12
UDB
...
Programmable
Digital
UDB
8x
S
er
ia
l C
om
m
(I
2
C
,SPI
,U
AR
T
,L
IN
,S
M
C
)
C
apS
e
nse
32
x
T
C
P
W
M
(T
IM
E
R
,C
T
R
,Q
D
, P
W
M
)
1x
S
er
ia
l C
om
m
(I
2C
,S
P
I,
D
eep
S
le
ep
)
DAC
(12-bit)
SAR ADC
(12-bit)
x1
CTB/CTBm
x1
2x OpAmp
Programmable
Analog
x1
SARMUX
LP
C
om
p
ar
at
or
Port Interface & Digital System Interconnect (DSI)
High Speed I /O Matrix , Smart I/O, Boundary Scan
I2
S
M
a
st
e
r/
S
la
ve
PD
M
/PC
M
Audio
Subsystem
LC
D
DataWire/
DMA
2x 16 Ch
Initiator/MMIO
WCO
RTC
BREG
Backup
Backup Control
Digital DFT
Test
Analog DFT
System Resources
Power
Reset
Sleep Control
PWRSYS-LP /ULP
REF
Reset Control
TestMode Entry
XRES
DeepSleep
Hibernate
Power Modes
Backup
Active/Sleep
LowePowerActive/Sleep
Buck
POR
LVD
BOD
OVP
Clock
Clock Control
IMO
WDT
CSV
1xPLL
ECO
ILO
FLL