CY7C656xx
PRELIMINARY
Document #: 38-08037 Rev. *D
Page 3 of 23
Figure 3-2. CY7C65630/CY7C65620 Block Diagram
3.0
Block Diagrams
(continued)
T his applies to C Y7C 65630 only.
Routing Logic
H ub R epeater
U SB U pstream Port
U SB 2.0 PH Y
PLL
Serial
Interface
Engine
H igh-Speed
U SB C ontr ol Logic
SPI C om m unication
Block
U SB D ow nstream Port 1
US B 2.0
P HY
P ort P ower
Control
P ort
S tatus
U SB D ow nstream Port 2
US B 2.0
P HY
P ort P ower
Control
P ort
S tatus
U SB D ow nstream Port 3
US B 2.0
P HY
P ort P ower
Control
P ort
S tatus
U SB D ow nstream Por t 4
US B 2.0
P HY
P ort P ower
Control
P ort
S tatus
S P I_S CK
S P I_CS
S P I_S D
D+
D-
P W R#[4]
OV R#[4]
LE D
D+
D- P W R#[3]
OV R#[3]
LE D
D+
D- P W R#[2]
OV R#[2]
LE D
D+
D- P W R#[1]
OV R#[1]
LE D
T ransaction Translator (X1)
TT RA M
D +
D -
24 M Hz
Cry s tal
