background image

CY7C1510JV18, CY7C1525JV18
CY7C1512JV18, CY7C1514JV18

Document #: 001-14435 Rev. *C

Page 7 of 26

CQ

Echo Clock

CQ is Referenced with Respect to C

. This is a free-running clock and is synchronized to the input clock 

for output data (C) of the QDR-II. In single clock mode, CQ is generated with respect to K. The timing for 
the echo clocks is shown in 

Switching Characteristics

 on page 22.

CQ

Echo Clock

CQ is Referenced with Respect to C

. This is a free-running clock and is synchronized to the input clock 

for output data (C) of the QDR-II. In single clock mode, CQ is generated with respect to K. The timing for 
the echo clocks is shown in the 

Switching Characteristics

 on page 22.

ZQ

Input

Output Impedance Matching Input

. This input is used to tune the device outputs to the system data bus 

impedance. CQ, CQ, and Q

[x:0] 

output impedance are set to 0.2 x RQ, where RQ is a resistor connected 

between ZQ and ground. Alternatively, connect this pin directly to V

DDQ

, which enables the minimum 

impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

DLL Turn Off 

 Active LOW

. Connecting this pin to ground turns off the DLL inside the device. The timing 

in the operation with the DLL turned off differs from those listed in this data sheet. For normal operation, 
connect this pin to a pull up through a 10 K

Ω

 or less pull up resistor. The device behaves in QDR-I mode 

when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz 
with QDR-I timing. 

TDO

Output

TDO for JTAG

.

TCK

Input

TCK Pin for JTAG

.

TDI

Input

TDI Pin for JTAG

.

TMS

Input

TMS Pin for JTAG

.

NC

N/A

Not Connected to the Die

. Can be tied to any voltage level.

V

SS

/144M

Input

Not Connected to the Die

. Can be tied to any voltage level.

V

SS

/288M

Input

Not Connected to the Die

. Can be tied to any voltage level.

V

REF

Input-

Reference

Reference Voltage Input

. Static input used to set the reference level for HSTL inputs, outputs, and AC 

measurement points.

V

DD

Power Supply

Power Supply Inputs to the Core of the Device

V

SS

Ground

Ground for the Device

V

DDQ

Power Supply

Power Supply Inputs for the Outputs of the Device

.

Pin Definitions 

 (continued)

Pin Name

IO

Pin Description

[+] Feedback 

[+] Feedback 

Summary of Contents for CY7C1510JV18

Page 1: ...ynchronous Pipelined SRAMs equipped with QDR II architecture QDR II architecture consists of two separate ports the read port and the write port to access the memory array The read port has dedicated...

Page 2: ...ta Reg RPS WPS Control Logic Address Register Reg Reg Reg 8 22 16 8 NWS 1 0 VREF Write Add Decode Write Reg 8 A 21 0 22 CQ CQ DOFF Q 7 0 8 8 8 Write Reg C C 4M x 8 Array 2M x 9 Array CLK A 20 0 Gen K...

Page 3: ...S WPS Control Logic Address Register Reg Reg Reg 18 21 36 18 BWS 1 0 VREF Write Add Decode Write Reg 18 A 20 0 21 CQ CQ DOFF Q 17 0 18 18 18 Write Reg C C 2M x 18 Array 1M x 36 Array CLK A 19 0 Gen K...

Page 4: ...Q VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1525JV18 8M x 9 1 2 3 4 5 6 7 8...

Page 5: ...0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1514JV18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M A WPS BWS2 K BWS1 RPS A NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A A A VSS D...

Page 6: ...rrays each of 4M x 8 for CY7C1510JV18 8M x 9 2 arrays each of 4M x 9 for CY7C1525JV18 4M x 18 2 arrays each of 2M x 18 for CY7C1512JV18 and 2M x 36 2 arrays each of 1M x 36 for CY7C1514JV18 Therefore...

Page 7: ...cannot be connected directly to GND or left unconnected DOFF Input DLL Turn Off Active LOW Connecting this pin to ground turns off the DLL inside the device The timing in the operation with the DLL t...

Page 8: ...rising edge of the positive input clock K On the same K clock rise the data presented to D 17 0 is latched and stored into the lower 18 bit write data register provided BWS 1 0 are both asserted activ...

Page 9: ...DLL is locked after 1024 cycles of stable clock The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns However it is not necessary to reset the DLL to lock t...

Page 10: ...written into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1510JV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C15...

Page 11: ...the device D 35 9 remains unaltered L H H H L H During the Data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the Data p...

Page 12: ...e of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Control...

Page 13: ...gister After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an...

Page 14: ...r follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN CAPT...

Page 15: ...oltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 Instructi...

Page 16: ...DI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2...

Page 17: ...ction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO Thi...

Page 18: ...5 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 4...

Page 19: ...e stable power and clock K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL func...

Page 20: ...12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V...

Page 21: ...eters Parameter Description Test Conditions 165 FBGA Package Unit JA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance...

Page 22: ...45 0 45 ns tCQOH tCHCQX Echo Clock Hold after C C Clock Rise 0 45 0 45 ns tCQD tCQHQV Echo Clock High to Data Valid 0 27 0 30 ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 27 0 30 ns tCQH tCQHCQ...

Page 23: ...1 D31 D11 D10 D60 Q C C DON T CARE UNDEFINED t CQ CQ tKHCH tCO tKHCH tCLZ CHZ tKH tKL Q00 Q01 Q20 tKHKH tCYC Q21 Q40 Q41 tCQD tDOH tCCQO tCQOH tCCQO tCQOH tCQDOH tCQH tCQHCQH Notes 25 Q00 refers to ou...

Page 24: ...Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1525JV18 267BZI CY7C1512JV18 267BZI CY7C1514JV18 267BZI CY7C1510JV18 267BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Fre...

Page 25: ...5 M C A B 0 05 M C B A 0 15 4X 0 35 0 06 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3...

Page 26: ...for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreemen...

Reviews: