Cypress Semiconductor CY7C1470V25 Specification Sheet Download Page 22

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CY7C1470V25
CY7C1472V25
CY7C1474V25

Document #: 38-05290 Rev. *I

Page 22 of 28

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit

www.cypress.com

for actual products offered.

Speed

(MHz)

Ordering Code

Package
Diagram

Part and Package Type

Operating

Range

167

CY7C1470V25-167AXC

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1472V25-167AXC

CY7C1470V25-167BZC

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)

CY7C1472V25-167BZC

CY7C1470V25-167BZXC

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free

CY7C1472V25-167BZXC

CY7C1474V25-167BGC

51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1474V25-167BGXC

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

CY7C1470V25-167AXI

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

lndustrial

CY7C1472V25-167AXI

CY7C1470V25-167BZI

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)

CY7C1472V25-167BZI

CY7C1470V25-167BZXI

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free

CY7C1472V25-167BZXI

CY7C1474V25-167BGI

51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1474V25-167BGXI

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

200

CY7C1470V25-200AXC

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1472V25-200AXC

CY7C1470V25-200BZC

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)

CY7C1472V25-200BZC

CY7C1470V25-200BZXC

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free

CY7C1472V25-200BZXC

CY7C1474V25-200BGC

51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1474V25-200BGXC

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

CY7C1470V25-200AXI

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

lndustrial

CY7C1472V25-200AXI

CY7C1470V25-200BZI

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)

CY7C1472V25-200BZI

CY7C1470V25-200BZXI

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free

CY7C1472V25-200BZXI

CY7C1474V25-200BGI

51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1474V25-200BGXI

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

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Summary of Contents for CY7C1470V25

Page 1: ...equired to enable consec utive Read Write operations with data being transferred on every clock cycle This feature dramatically improves the throughput of data in systems that require frequent Write R...

Page 2: ...am CY7C1472V25 4M x 18 Logic Block Diagram CY7C1474V25 1M x 72 A0 A1 A C MODE CE1 CE2 CE3 OE READ LOGIC DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh D A T A S T E E R I N G O U T P U T B U F F E R S ME...

Page 3: ...Z CY7C1470V25 100 pin TQFP Pinout A A A A A 1 A 0 V SS V DD A A A A A A A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS...

Page 4: ...D NC VDD DQa VDD VDDQ DQa VDDQ VDD VDD VDDQ VDD VDDQ DQa VDDQ A A VSS A A A DQb DQb DQb ZZ DQa DQa DQPa DQa A VDDQ A 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPb NC DQb A C...

Page 5: ...VSS VSS VSS ZZ VSS VSS VSS VSS NC VDDQ VSS VSS NC VSS VSS VSS VSS VSS VSS NC VSS VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ...

Page 6: ...by A 18 0 during the previous clock rise of the read cycle The direction of the pins is controlled by OE and the internal control logic When OE is asserted LOW the pins can behave as outputs When HIGH...

Page 7: ...and A1 in the burst sequence and will wrap around when incre mented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enables inputs or WE...

Page 8: ...rameter is sampled 0 ns Truth Table 1 2 3 4 5 6 7 Operation Address Used CE ZZ ADV LD WE BWx OE CEN CLK DQ Deselect Cycle None H L L X X X L L H Tri State Continue Deselect Cycle None X L H X X X L L...

Page 9: ...Write Bytes d a L L H H L Write Bytes d b L L H L H Write Bytes d b a L L H L L Write Bytes d c L L L H H Write Bytes d c a L L L H L Write Bytes d c b L L L L H Write All Bytes L L L L L Function CY7...

Page 10: ...ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the regi...

Page 11: ...SAMPLE PRELOAD rather it performs a capture of the I O ring when these instructions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register...

Page 12: ...n a board Reserved These instructions are not implemented but are reserved for future use Do not use these instructions TAP Timing t TL Test Clock TCK 1 2 3 4 5 6 Test Mode Select TMS tTH Test Data Ou...

Page 13: ...H2 Output HIGH Voltage IOH 100 A VDDQ 2 5V 2 1 V VDDQ 1 8V 1 6 V VOL1 Output LOW Voltage IOL 1 0 mA VDDQ 2 5V 0 4 V VOL2 Output LOW Voltage IOL 100 A VDDQ 2 5V 0 2 V VDDQ 1 8V 0 2 V VIH Input HIGH Vol...

Page 14: ...between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures I O ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a Hi...

Page 15: ...31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 Bounda...

Page 16: ...A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4...

Page 17: ...O 1 26 VDD 0 3V V VIL Input LOW Voltage 12 for 2 5V I O 0 3 0 7 V for 1 8V I O 0 3 0 36 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A Input VDD 5...

Page 18: ...e 209 FBGA Package Unit JA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 24 63 16 3 15 2 C W JC Ther...

Page 19: ...ip Select Set up 1 4 1 4 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 4 0 4 0 5 ns tDH Data Input Hold After CLK Rise 0 4 0 4 0 5 ns tCENH CEN Hold After CLK Rise 0 4 0 4 0 5 ns tWEH WE BWx Hol...

Page 20: ...e Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK t CYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BWx ADV...

Page 21: ...ode See cycle description table for all possible signal conditions to deselect the device 26 I Os are in High Z when exiting ZZ sleep mode Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 CLK CE...

Page 22: ...1470V25 167BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4mm Lead Free CY7C1472V25 167BZXI CY7C1474V25 167BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C1474V25 167...

Page 23: ...C1470V25 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1472V25 250AXI CY7C1470V25 250BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1472V...

Page 24: ...NSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND O...

Page 25: ...1 00 0 45 0 05 165X 0 25 M C A B 0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 1...

Page 26: ...press written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expecte...

Page 27: ...DQb DQb DQb to DQPa DQa DQa DQa DQa in page 4 Modified capacitance values in page 19 E 299511 See ECN SYT Removed 225 MHz offering and included 250 MHz speed bin Changed tCYC from 4 4 ns to 4 0 ns fo...

Page 28: ...r H9 to VSS from VSSQ Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Upd...

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