Cypress Semiconductor CY7C1381DV25 Specification Sheet Download Page 26

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CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Document #: 38-05547 Rev. *E

Page 26 of 28

Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

Package Diagrams

(continued)

51-85115-*B

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Summary of Contents for CY7C1381DV25

Page 1: ...d by a positive edge triggered clock input CLK The synchronous inputs include all addresses all data inputs address pipelining chip enable CE1 depth expansion chip enables CE2 and CE3 2 burst control inputs ADSC ADSP and ADV write enables BWx and BWE and global write GW Asynchronous inputs include the output enable OE and the ZZ pin The CY7C1381DV25 CY7C1383DV25 CY7C1381FV25 CY7C1383FV25 allows in...

Page 2: ... B BW A BWE CE1 CE2 CE3 OE GW SLEEP DQA DQP A BYTE WRITE REGISTER DQB DQP B WRITE REGISTER DQC DQP C WRITE REGISTER BYTE WRITE REGISTER DQD DQP D BYTE WRITE REGISTER DQD DQP D BYTE WRITE REGISTER DQC DQP C WRITE REGISTER DQB DQP B WRITE REGISTER DQA DQP BYTE WRITE REGISTER ADDRESS REGISTER ADV BURST COUNTER AND Q1 Q0 CE 1 OE SENSE AMPS MEMORY ARRAY OUTPUT BUFFERS INPUT REGISTERS MODE CE 2 CE 3 GW ...

Page 3: ...67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 MODE CY7C1381DV25 512K x 36 NC A A A A A 1 A 0 NC NC V SS V DD A A A A A A A A A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB...

Page 4: ... DQC VDD DQD DQD DQD DQD ADSC NC CE1 OE ADV GW VSS VSS VSS VSS VSS VSS VSS VSS DQPA MODE DQPD DQPB BWB BWC NC VDD NC BWA NC BWE BWD ZZ 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R T U VDDQ NC 288M NC 144M NC DQB DQB DQB DQB A A A A ADSP VDDQ A A NC VDDQ NC VDDQ VDDQ VDDQ NC NC NC NC 72M VDDQ VDD CLK VDD VSS VSS VSS VSS VSS VSS VSS VSS NC 576M NC 1G NC NC TDO TCK TDI TMS A A NC VDDQ VDDQ VDDQ A NC 3...

Page 5: ...VDD DQB DQB DQB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A CY7C1383DV25 1Mx 18 A0 A VSS 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 288M NC 144M NC NC DQPB VSS DQB A CE1 NC CE3 BWB BWE A CE2 NC DQB DQB MODE NC DQB DQB NC NC NC NC 36M NC 72M VDDQ NC BWA CLK GW VSS VSS VSS VSS V...

Page 6: ...ing from a deselected state ADV Input Synchronous Advance input signal Sampled on the rising edge of CLK When asserted it automatically increments the address in a burst cycle ADSP Input Synchronous Address strobe from processor sampled on the rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers A 1 0 are also loaded into the burst...

Page 7: ...access is initiated when the following conditions are satisfied at clock rise 1 CE1 CE2 CE3 2 are all asserted active and 2 ADSP is asserted LOW The addresses presented are loaded into the address register and the burst inputs GW BWE and BWX are ignored during this first clock cycle If the write inputs are asserted active see Truth Table for Read Write 4 9 on page 10 for appropriate states that in...

Page 8: ... and can follow either a linear or interleaved burst order The burst order is determined by the state of the MODE input A LOW on MODE will select a linear burst sequence A HIGH on MODE will select an interleaved burst order Leaving MODE unconnected will cause the device to default to a interleaved burst sequence Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a...

Page 9: ...L L X L H D Write Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H X X L X H H H L L H Q Read Cycle Suspend Burst Current H X X L X H H H H L H Tri State Write Cycle Suspend Burst Current X X X L H H H L X L H D Write Cycle Suspend Burst Curr...

Page 10: ... D A DQD DQA DQPD DQPA H L L H H L Write Bytes D B DQD DQA DQPD DQPA H L L H L H Write Bytes D B A DQD DQB DQA DQPD DQPB DQPA H L L H L L Write Bytes D B DQD DQB DQPD DQPB H L L L H H Write Bytes D B A DQD DQC DQA DQPD DQPC DQPA H L L L H L Write Bytes D C A DQD DQB DQA DQPD DQPB DQPA H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read Write 4 9 Function CY7C13...

Page 11: ...internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See TAP Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TD...

Page 12: ...s the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state Th...

Page 13: ...rved These instructions are not implemented but are reserved for future use Do not use these instructions TAP Timing TAP AC Switching Characteristics Over the Operating Range 10 11 Parameter Description Min Max Unit Clock tTCYC TCK Clock Cycle Time 50 ns tTF TCK Clock Frequency 20 MHz tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTD...

Page 14: ... Voltage VDDQ 2 5V 0 3 0 7 V IX Input Load Current GND VIN VDDQ 5 5 µA Identification Register Definitions Instruction Field CY7C1381DV25 CY7C1381FV25 512K x 36 CY7C1383DV25 CY7C1383FV25 1 Mbit x 18 Description Revision Number 31 29 000 000 Describes the version number Device Depth 28 24 01011 01011 Reserved for internal use Device Width 23 18 119 BGA 101001 101001 Defines the memory type and arch...

Page 15: ...fect SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations 119 Ball BGA Boundary Scan Order 13 14 Bit Ball ID Bit Ball ID Bit Ball ID Bit Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 2...

Page 16: ...7 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1...

Page 17: ... IO 1 7 VDD 0 3V V VIL Input LOW Voltage 16 for 2 5V IO 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDD Output Disabled 5 5 µA IDD VDD Operating Supply Current VDD Max IOUT 0 mA f fMAX 1 tCYC 7 5 ns cycle 133 MHz 210 mA 10 ns cycle 1...

Page 18: ...ons 100 TQFP Package 119 BGA Package 165 FBGA Package Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 28 66 23 8 20 7 C W ΘJC Thermal Resistance Junction to Case 4 08 6 2 4 0 C W AC Test Loads and Waveforms OUTPUT R 1667Ω R 1538Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL 50Ω Z...

Page 19: ... Times tAH Address Hold After CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Chip Enable Hold After CLK Rise 0 5 0 5 ns Notes 19 Timing reference level is 1 25V 20 Test conditions shown in a of AC Test Loads unless otherwise noted 21 This ...

Page 20: ...tDOH tCDV tOEHZ tCDV SingleREAD BURST READ tOEV tOELZ tCHZ Burstwrapsaround toitsinitialstate t ADVH t ADVS t WEH t WES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A2 2 Q A2 3 A2 ADVsuspendsburst DeselectCycle DON TCARE UNDEFINED ADSP ADSC GW BWE BW X CE ADV OE Note 25 On this diagram when CE is LOW CE1 is LOW CE2 is HIGH and CE3 is LOW When CE is HIGH CE1 is HIGH or CE2 is LOW or CE3 is HIGH ...

Page 21: ... D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS tWEH tWES t DH t DS t WEH t WES Byte write signals are ignored for ﬁrst cycle when ADSP initiates burst ADSC extends burst ADV suspends burst DON T CARE UNDEFINED ADSP ADSC BWE BW X GW CE ADV OE Data in D Data Out Q Note 26 Full width write can be initiated by either GW LOW ...

Page 22: ... tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1 Q A4 2 Q A4 3 t WEH t WES t OEHZ tDH tDS tCDV tOELZ A1 A5 A6 D A5 D A6 Q A1 Back to Back WRITEs DON T CARE UNDEFINED ADSP ADSC BWE BW X CE ADV OE Data In D Data Out Q Notes 27 The data bus Q remains in high Z following a write cycle unless a new read access is initiated by ADSP or ADSC 28 GW is HIGH Feedback ...

Page 23: ...ntinued tZZ I SUPPLY CLK ZZ tZZREC ALL INPUTS except ZZ DON T CARE I DDZZ tZZI tRZZI Outputs Q High Z DESELECT or READ Only Notes 29 Device must be deselected when entering ZZ sleep mode See Cycle Descriptions table for all possible signal conditions to deselect the device 30 DQs are in high Z when exiting ZZ sleep mode Feedback ...

Page 24: ...ll Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1383FV25 133BGXI CY7C1381DV25 133BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1383DV25 133BZI CY7C1381DV25 133BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1383DV25 133BZXI 100 CY7C1381DV25 100AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1383DV25 100AXC CY7C1381F...

Page 25: ...OLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 31...

Page 26: ...CY7C1381DV25 CY7C1381FV25 CY7C1383DV25 CY7C1383FV25 Document 38 05547 Rev E Page 26 of 28 Figure 2 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 Package Diagrams continued 51 85115 B Feedback ...

Page 27: ...6 is a trademark of Intel Corporation All product and company names mentioned in this document are the trademarks of their respective holders Figure 3 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 Package Diagrams continued A 1 PIN 1 CORNER 15 00 0 10 13 00 0 10 7 00 1 00 Ø0 50 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 ...

Page 28: ...ly Changed ΘJA and ΘJc or BGA Package from 45 and 7 C W to 23 8 and 6 2 C W respectively Changed ΘJA and ΘJc for FBGA Package from 46 and 3 C W to 20 7 and 4 0 C W respectively Modified VOL VOH test conditions Removed comment of Pb free BG packages availability below the Ordering Information Updated Ordering Information Table C 416321 See ECN NXR Changed address of Cypress Semiconductor Corporatio...

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