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CY7C138, CY7C139

Document #: 38-06037  Rev. *D

Page 6 of 17

t

HD

Data Hold From Write End

0

0

0

0

ns

t

HZWE

[11,12]

R/W LOW to High Z

10

15

20

25

ns

t

LZWE

[11,12]

R/W HIGH to Low Z

3

3

3

3

ns

t

WDD

[13]

Write Pulse to Data Delay

30

50

60

70

ns

t

DDD

[13]

Write Data Valid to Read Data Valid

25

30

35

40

ns

BUSY TIMING

[14]

t

BLA

BUSY LOW from Address Match

15

20

20

45

ns

t

BHA

BUSY HIGH from Address Mismatch

15

20

20

40

ns

t

BLC

BUSY LOW from CE LOW

15

20

20

40

ns

t

BHC

BUSY HIGH from CE HIGH

15

20

20

35

ns

t

PS

Port Set-Up for Priority

5

5

5

5

ns

t

WB

R/W LOW after BUSY LOW

0

0

0

0

ns

t

WH

R/W HIGH after BUSY HIGH

13

20

30

40

ns

t

BDD

[15]

BUSY HIGH to Data Valid

Note 15

Note 15

Note 15

Note 15

ns

INTERRUPT TIMING

[14]

t

INS

INT Set Time

15

25

25

30

ns

t

INR

INT Reset Time

15

25

25

30

ns

SEMAPHORE TIMING

t

SOP

SEM Flag Update Pulse (OE or SEM)

10

10

15

20

ns

t

SWRD

SEM Flag Write to Read Time

5

5

5

5

ns

t

SPS

SEM Flag Contention Window

5

5

5

5

ns

Switching Characteristics 

Over the Operating Range

[9]

 (continued)

Parameter

Description

7C138-15

7C139-15

7C138-25

7C139-25

7C138-35

7C139-35

7C138-55

7C139-55

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Notes

9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified 

I

OI

/I

OH

 and 30-pF load capacitance.

10. At any given temperature and voltage condition for any given device, t

HZCE

 is less than t

LZCE

 and t

HZOE

 is less than t

LZOE

.

11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
15. t

BDD

 is a calculated parameter and is the greater of t

WDD

 – t

PWE

 (actual) or t

DDD

 – t

SD

 (actual).

Switching Waveforms 

Figure 3.  Read Cycle No. 1 (Either Port Address Access)

[16, 17]

Figure 4.  Read Cycle No. 2 (Either Port CE/OE Access)

[16, 18, 19]

t

RC

t

AA

t

OHA

DATA VALID

PREVIOUS DATA VALID

DATA OUT

ADDRESS

[+] Feedback 

Summary of Contents for CY7C138

Page 1: ...9 bit dual port static RAM or multiple devices can be combined to function as a 16 18 bit or wider master slave dual port static RAM An M S pin is provided for implementing 16 18 bit or wider memory a...

Page 2: ...leared when right port reads location FFF BUSYL BUSYR Busy Flag M S Master or Slave Select VCC Power GND Ground 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 67 60 59 58 57 56 55 54 53 52 51 50 49 48 3...

Page 3: ...4 0 mA 0 4 0 4 V VIH 2 2 2 2 V VIL Input LOW Voltage 0 8 0 8 V IIX Input Leakage Current GND VI VCC 10 10 10 10 A IOZ Output Leakage Current Output Disabled GND VO VCC 10 10 10 10 A ICC Operating Curr...

Page 4: ...uts Disabled Commercial 160 160 mA Industrial 180 180 ISB1 Standby Current Both Ports TTL Levels CEL and CER VIH f fMAX 7 Commercial 30 30 mA Industrial 40 40 ISB2 Standby Current One Port TTL Level C...

Page 5: ...Max Min Max READ CYCLE tRC Read Cycle Time 15 25 35 55 ns tAA Address to Data Valid 15 25 35 55 ns tOHA Output Hold From Address Change 3 3 3 3 ns tACE CE LOW to Data Valid 15 25 35 55 ns tDOE OE LOW...

Page 6: ...indow 5 5 5 5 ns Switching Characteristics Over the Operating Range 9 continued Parameter Description 7C138 15 7C139 15 7C138 25 7C139 25 7C138 35 7C139 35 7C138 55 7C139 55 Unit Min Max Min Max Min M...

Page 7: ...HZCE DATA VALID DATA OUT SEM or CE OE tLZCE tPU ICC ISB tPD VALID tDDD tWDD MATCH MATCH R WR DATA INR DATAOUTL tWC ADDRESSR t PWE VALID t SD t HD ADDRESSL Notes 16 R W is HIGH for read cycle 17 Device...

Page 8: ...e time of the memory is defined by the overlap of CE or SEM LOW and R W LOW Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH The data input set up and...

Page 9: ...ntinued tSOP tAA SEM R W OE I O0 VALID ADDRESS VALID ADDRESS tHD DATAIN VALID DATAOUT VALID tOHA A0 A 2 tAW tHA tACE tSOP tSCE tSD tSA tPWE tSWRD tDOE WRITE CYCLE READ CYCLE MATCH tSPS A0L A2L MATCH R...

Page 10: ...ts at cycle start 29 If tSPS is violated the semaphore will definitely be obtained by one side or the other but there is no guarantee which side will control the semaphore Figure 12 Busy Timing Diagra...

Page 11: ...n which side BUSY will be asserted Switching Waveforms continued ADDRESS MATCH tPS tBLC tBHC ADDRESS MATCH tPS tBLC tBHC ADDRESSL R BUSYR CEL CER BUSY L CER CEL ADDRESSL R CEL Valid First CER Valid Fi...

Page 12: ...nds on which enable pin CEL or R WL is asserted last Switching Waveforms continued WRITE FFF tWC tHA READ FFF tRC tINR WRITE FFE tWC READ FFE tINR tRC ADDRESSR CE L R WL INTL OE L ADDRESSR R WR CER IN...

Page 13: ...g the device as either a master or a slave The BUSY output of the master is connected to the BUSY input of the slave This enables the device to interface to a master device with no external components...

Page 14: ...X L L FFF H Table 5 Semaphore Operation Example Function I O0 7 8 Left I O0 7 8 Right Status No action 1 1 Semaphore free Left port writes semaphore 0 1 Left port obtains semaphore Right port writes...

Page 15: ...1 0 0 9 4 0 4 5 5 0 5 5 6 0 NORMALIZED t AA SUPPLY VOLTAGE V NORMALIZED ACCESS TIME vs SUPPLY VOLTAGE 120 140 100 60 40 20 0 0 1 0 2 0 3 0 4 0 OUTPUT SINK CURRENT mA 0 80 OUTPUT VOLTAGE V OUTPUT SINK...

Page 16: ...ercial CY7C138 25JXC J81 68 Lead Pb Free Plastic Leaded Chip Carrier CY7C138 25JI J81 68 Lead Plastic Leaded Chip Carrier Industrial CY7C138 25JXI J81 68 Lead Pb Free Plastic Leaded Chip Carrier 35 CY...

Page 17: ...Y OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to...

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