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CY7C138, CY7C139

4K x 8/9 Dual-Port Static RAM

with Sem, Int, Busy

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document #: 38-06037  Rev. *D

 Revised March 12, 2009

Features

True Dual-Ported memory cells that enable simultaneous reads 

of the same memory location

4K x 8 organization (CY7C138)

4K x 9 organization (CY7C139)

0.65-micron CMOS for optimum speed and power

High speed access: 15 ns

Low operating power: I

CC

 = 160 mA (max.)

Fully asynchronous operation

Automatic power down

TTL compatible

Expandable data bus to 32/36 bits or more using 

Master/Slave chip select when using more than one 

device

On-chip arbitration logic

Semaphores included to permit software handshaking 

between ports 

INT flag for port-to-port communication

Available in 68-pin PLCC

Pb-free packages available

Functional Description

The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and

4K x 9 dual-port static RAMs. Various arbitration schemes are

included on the CY7C138/9 to handle situations when multiple

processors access the same piece of data. Two ports are

provided permitting independent, asynchronous access for

reads and writes to any location in memory. The CY7C138/9 can

be used as a standalone 8/9-bit dual-port static RAM or multiple

devices can be combined to function as a 16/18-bit or wider

master/slave dual-port static RAM. An M/S pin is provided for

implementing 16/18-bit or wider memory applications without the

need for separate master and slave devices or additional

discrete logic. Application areas include interprocessor/multipro-

cessor designs, communications status buffering, and dual-port

video/graphics memory. 
Each port has independent control pins: chip enable (CE), read

or write enable (R/W), and output enable (OE). Two flags are

provided on each port (BUSY and INT). BUSY signals that the

port is trying to access the same location currently being

accessed by the other port. The interrupt flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from one

port to the other to indicate that a shared resource is in use. The

semaphore logic is comprised of eight shared latches. Only one

side can control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power down feature is controlled independently on

each port by a chip enable (CE) pin or SEM pin.
The CY7C138 and CY7C139 are available in a 68-pin PLCC.

Notes

1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.

Logic Block Diagram

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Summary of Contents for CY7C138

Page 1: ...9 bit dual port static RAM or multiple devices can be combined to function as a 16 18 bit or wider master slave dual port static RAM An M S pin is provided for implementing 16 18 bit or wider memory a...

Page 2: ...leared when right port reads location FFF BUSYL BUSYR Busy Flag M S Master or Slave Select VCC Power GND Ground 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 67 60 59 58 57 56 55 54 53 52 51 50 49 48 3...

Page 3: ...4 0 mA 0 4 0 4 V VIH 2 2 2 2 V VIL Input LOW Voltage 0 8 0 8 V IIX Input Leakage Current GND VI VCC 10 10 10 10 A IOZ Output Leakage Current Output Disabled GND VO VCC 10 10 10 10 A ICC Operating Curr...

Page 4: ...uts Disabled Commercial 160 160 mA Industrial 180 180 ISB1 Standby Current Both Ports TTL Levels CEL and CER VIH f fMAX 7 Commercial 30 30 mA Industrial 40 40 ISB2 Standby Current One Port TTL Level C...

Page 5: ...Max Min Max READ CYCLE tRC Read Cycle Time 15 25 35 55 ns tAA Address to Data Valid 15 25 35 55 ns tOHA Output Hold From Address Change 3 3 3 3 ns tACE CE LOW to Data Valid 15 25 35 55 ns tDOE OE LOW...

Page 6: ...indow 5 5 5 5 ns Switching Characteristics Over the Operating Range 9 continued Parameter Description 7C138 15 7C139 15 7C138 25 7C139 25 7C138 35 7C139 35 7C138 55 7C139 55 Unit Min Max Min Max Min M...

Page 7: ...HZCE DATA VALID DATA OUT SEM or CE OE tLZCE tPU ICC ISB tPD VALID tDDD tWDD MATCH MATCH R WR DATA INR DATAOUTL tWC ADDRESSR t PWE VALID t SD t HD ADDRESSL Notes 16 R W is HIGH for read cycle 17 Device...

Page 8: ...e time of the memory is defined by the overlap of CE or SEM LOW and R W LOW Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH The data input set up and...

Page 9: ...ntinued tSOP tAA SEM R W OE I O0 VALID ADDRESS VALID ADDRESS tHD DATAIN VALID DATAOUT VALID tOHA A0 A 2 tAW tHA tACE tSOP tSCE tSD tSA tPWE tSWRD tDOE WRITE CYCLE READ CYCLE MATCH tSPS A0L A2L MATCH R...

Page 10: ...ts at cycle start 29 If tSPS is violated the semaphore will definitely be obtained by one side or the other but there is no guarantee which side will control the semaphore Figure 12 Busy Timing Diagra...

Page 11: ...n which side BUSY will be asserted Switching Waveforms continued ADDRESS MATCH tPS tBLC tBHC ADDRESS MATCH tPS tBLC tBHC ADDRESSL R BUSYR CEL CER BUSY L CER CEL ADDRESSL R CEL Valid First CER Valid Fi...

Page 12: ...nds on which enable pin CEL or R WL is asserted last Switching Waveforms continued WRITE FFF tWC tHA READ FFF tRC tINR WRITE FFE tWC READ FFE tINR tRC ADDRESSR CE L R WL INTL OE L ADDRESSR R WR CER IN...

Page 13: ...g the device as either a master or a slave The BUSY output of the master is connected to the BUSY input of the slave This enables the device to interface to a master device with no external components...

Page 14: ...X L L FFF H Table 5 Semaphore Operation Example Function I O0 7 8 Left I O0 7 8 Right Status No action 1 1 Semaphore free Left port writes semaphore 0 1 Left port obtains semaphore Right port writes...

Page 15: ...1 0 0 9 4 0 4 5 5 0 5 5 6 0 NORMALIZED t AA SUPPLY VOLTAGE V NORMALIZED ACCESS TIME vs SUPPLY VOLTAGE 120 140 100 60 40 20 0 0 1 0 2 0 3 0 4 0 OUTPUT SINK CURRENT mA 0 80 OUTPUT VOLTAGE V OUTPUT SINK...

Page 16: ...ercial CY7C138 25JXC J81 68 Lead Pb Free Plastic Leaded Chip Carrier CY7C138 25JI J81 68 Lead Plastic Leaded Chip Carrier Industrial CY7C138 25JXI J81 68 Lead Pb Free Plastic Leaded Chip Carrier 35 CY...

Page 17: ...Y OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to...

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