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Cypress Semiconductor CY7C1354CV25, Specification Sheet

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Cypress Semiconductor CY7C1354CV25 Specification Sheet Download Page 20

CY7C1354CV25
CY7C1356CV25

Document #: 38-05537 Rev. *H

Page 20 of 28

NOP, STALL and DESELECT CYCLES

[23, 24, 26]

Note: 

26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

Switching Waveforms

 (continued)

READ

Q(A3)

4

5

6

7

8

9

10

CLK

CE

WE

CEN

BW

X

ADV/LD

ADDRESS

A3

A4

A5

D(A4)

 Data

 In-Out (DQ)

A1

Q(A5)

WRITE

D(A4)

STALL

WRITE

D(A1)

1

2

3

READ

Q(A2)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

t

CHZ

A2

D(A1)

Q(A2)

Q(A3)

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Summary of Contents for CY7C1354CV25

Page 1: ...dramatically improves the throughput of data in systems that require frequent Write Read transitions The CY7C1354CV25 and CY7C1356CV25 are pin compatible with and functionally equivalent to ZBT device...

Page 2: ...ER 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E INPUT REGISTER 1 S E N S E A M P S O U T P U T R E G I S T E R S E C...

Page 3: ...pin TQFP Pinout A A A A A 1 A 0 V SS V DD A A A A A A A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQb DQb VSS...

Page 4: ...NC 288M A A A1 A0 VSS VDD NC CY7C1354CV25 256K 36 DQPc DQb A NC 36M DQc DQb DQc DQc DQc DQb DQb DQa DQa DQa DQa DQPa DQd DQd DQd DQd BWd 119 Ball BGA Pinout BWb 2 3 4 5 6 7 1 A B C D E F G H J K L M N...

Page 5: ...VDD NC VDD DQa VDD VDDQ DQa VDDQ VDD VDD VDDQ VDD VDDQ DQa VDDQ A A VSS A A A DQb DQb DQb ZZ DQa DQa DQPa DQa A VDDQ A 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPb NC DQb...

Page 6: ...e first clock when emerging from a deselected state and when the device has been deselected CEN Input Synchronous Clock Enable Input active LOW When asserted LOW the clock signal is recognized by the...

Page 7: ...ave an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load...

Page 8: ...rst Address Table MODE Floating or VDD First Address Second Address Third Address Fourth Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE...

Page 9: ...a L H L H L Write Bytes c b L H L L H Write Bytes c b a L H L L L Write Byte d DQd and DQPd L L H H H Write Bytes d a L L H H L Write Bytes d b L L H L H Write Bytes d b a L L H L L Write Bytes d c L...

Page 10: ...ster between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see TAP Controller State Diagram TDI is inter...

Page 11: ...ODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan regist...

Page 12: ...tTMSS TMS Set up to TCK Clock Rise 5 ns tTDIS TDI Set up to TCK Clock Rise 5 ns tCS Capture Set up to TCK Rise 5 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise...

Page 13: ...ows unique identification of SRAM vendor ID Register Presence 0 1 1 Indicate the presence of an ID register Scan Register Sizes Register Name Bit Size x36 Bit Size x18 Instruction 3 3 Bypass 1 1 ID 32...

Page 14: ...24 M6 K11 25 L7 L11 26 K6 M11 27 P6 N11 28 T4 R11 29 A3 R10 30 C5 P10 31 B5 R9 32 A5 P9 33 C6 R8 34 A6 P8 35 P4 R6 36 N4 P6 37 R6 R4 38 T5 P4 39 T3 R3 40 R2 P3 41 R3 R1 42 P2 N1 43 P1 L2 44 L2 K2 45 K...

Page 15: ...P6 37 R6 R4 38 T5 P4 39 T3 R3 40 R2 P3 41 R3 R1 42 Not Bonded Preset to 0 Not Bonded Preset to 0 43 Not Bonded Preset to 0 Not Bonded Preset to 0 44 Not Bonded Preset to 0 Not Bonded Preset to 0 45 N...

Page 16: ...5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A Input VDD 5 A Input Current of ZZ Input VSS 5 A Input VDD 30 A IOZ Output Leakage Cu...

Page 17: ...0 TQFP Package 119 BGA Package 165 FBGA Package Unit JA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD5...

Page 18: ...5 ns tCES Chip Select Set up 1 4 1 5 1 5 ns Hold Times tAH Address Hold after CLK Rise 0 4 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 4 0 5 0 5 ns tCENH CEN Hold after CLK Rise 0 4 0 5 0 5 ns tW...

Page 19: ...rst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK t CYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BWX ADV LD t...

Page 20: ...illustrated CEN being used to create a pause A write is not performed during this cycle Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 CLK CE WE CEN BWX ADV LD ADDRESS A3 A4 A5 D A4 Data In Ou...

Page 21: ...ed when entering ZZ mode See cycle description table for all possible signal conditions to deselect the device 28 I Os are in High Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUP...

Page 22: ...x 22 x 2 4 mm Lead Free CY7C1356CV25 166BGXC CY7C1354CV25 166BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1356CV25 166BZC CY7C1354CV25 166BZXC 51 85180 165 ball Fine Pitch Ba...

Page 23: ...Lead Free CY7C1356CV25 200BZXC CY7C1354CV25 200AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1356CV25 200AXI CY7C1354CV25 200BGI 51 85115 119 ball Ball Grid Array...

Page 24: ...Lead Free CY7C1356CV25 250BZXC CY7C1354CV25 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1356CV25 250AXI CY7C1354CV25 250BGI 51 85115 119 ball Ball Grid Array...

Page 25: ...S IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R...

Page 26: ...F K J U P N M T R 12 00 19 50 30 TYP 2 40 MAX A1 CORNER 0 70 REF U T R P N M L K J H G F E D C A B 2 1 4 3 6 5 7 1 00 3X REF 7 62 22 00 0 20 14 00 0 20 1 27 0 60 0 10 C 0 15 C B A 0 15 4X 0 05 M C 0...

Page 27: ...The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Package Diagram...

Page 28: ...nsion as per JEDEC Standard Removed comment of Lead free BG and BZ packages availability D 332879 See ECN PCI Unshaded 200 and 166 MHz speed bin in the AC DC Table and Selection Guide Added Address Ex...

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