Cypress Semiconductor CY7C1345G Specification Sheet Download Page 15

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CY7C1345G

Document Number: 38-05517 Rev. *E

Page 15 of 20

Figure 3

shows the read and write timing.

[16, 17, 18]

Figure 3. Read/Write Timing

Timing Diagrams

(continued)

tCYC

CLK

tADH

tADS

ADDRESS

tAH

tAS

tCEH

tCES

Single WRITE

D(A3)

BURST READ

Back-to-Back READs

High-Z

Q(A2)

Q(A4)

Q(A4+1)

Q(A4+2)

Q(A4+3)

WEH

WES

OEHZ

tDH

tDS

tCDV

tOELZ

D(A5)

D(A6)

Q(A1)

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

ADSP

ADSC

BWE, BW

[A:B]

ADV

Data In (D)

Data Out (Q)

Notes:

17. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
18. GW is HIGH.

Summary of Contents for CY7C1345G

Page 1: ...positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE1 depth expansion Chip Enables CE2 and CE3 Burst Control inputs A...

Page 2: ...ARRAY MODE A 1 0 ZZ DQs DQP A DQP B DQP C DQP D A0 A1 A ADV CLK ADSP ADSC BW D BW C BW B BW A BWE CE1 CE2 CE3 OE GW SLEEP CONTROL DQA DQPA BYTE WRITE REGISTER DQB DQP B BYTE WRITE REGISTER DQC DQP C...

Page 3: ...VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK GW BWE OE ADSP A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18...

Page 4: ...Q CE2 A DQC VDDQ DQC VDDQ VDDQ VDDQ DQD DQD NC NC VDDQ VDD CLK VDD VSS VSS VSS VSS VSS VSS VSS VSS NC 576M NC 1G NC NC NC NC NC NC NC 36M NC 72M NC VDDQ VDDQ VDDQ A A A A CE3 A A A A A A A0 A1 DQA DQC...

Page 5: ...ols the direction of the IO pins When LOW the IO pins act as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when eme...

Page 6: ...W The addresses presented are loaded into the address register and the burst inputs GW BWE and BWx are ignored during this first clock cycle If the write inputs are asserted active see Write Cycle Des...

Page 7: ...e are not considered valid nor is the completion of the operation guaranteed The device is deselected prior to entering the sleep mode CEs ADSP and ADSC must remain inactive for the duration of tZZREC...

Page 8: ...rite Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burs...

Page 9: ...Bytes C B DQPC DQPB H L H L L H Write Bytes C B A DQPC DQPB DQPA H L H L L L Write Byte D DQPD H L L H H H Write Bytes D A DQPD DQPA H L L H H L Write Bytes D B DQPD DQPA H L L H L H Write Bytes D B A...

Page 10: ...0 3V V for 2 5V IO 1 7 VDD 0 3V V VIL Input LOW Voltage 7 for 3 3V IO 0 3 0 8 V for 2 5V IO 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30...

Page 11: ...ffect these parameters Parameter Description Test Conditions 100 TQFP Package 119 BGA Package Unit JA Thermal Resistance Junction to Ambient Test conditions follow standardtestmethodsand procedures fo...

Page 12: ...5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns tWEH GW BWE BWx Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Chip E...

Page 13: ...CLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its initial state t ADVH t ADVS t WEH t WES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A2 2 Q A2 3 A2 ADV sus...

Page 14: ...2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS tWEH tWES t DH t DS t WEH t WES Byte write signals are ignored for...

Page 15: ...tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1 Q A4 2 Q A4 3 t WEH t WES t OEHZ tDH tDS tCDV tOELZ A1 A5 A6 D A5 D A6 Q A1 Back to Back WRITEs DON T CA...

Page 16: ...iagrams continued t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI t RZZI Outputs Q High Z DESELECT or READ Only Notes 19 Device must be deselected when entering ZZ mode See T...

Page 17: ...19 Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1345G 133AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free lndustrial CY7C1345G 133BGI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7...

Page 18: ...ND FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05...

Page 19: ...ued 1 27 20 32 2 1 6 5 4 3 7 L E A B D C H G F K J U P N M T R 12 00 19 50 30 TYP 2 40 MAX A1 CORNER 0 70 REF U T R P N M L K J H G F E D C A B 2 1 4 3 6 5 7 1 00 3X REF 7 62 22 00 0 20 14 00 0 20 1 2...

Page 20: ...ITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does...

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