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Cypress Semiconductor CY7C1316CV18, Specification Sheet

The Cypress Semiconductor CY7C1316CV18 is a high-performance integrated circuit that offers a wide range of features for various applications. To fully explore its capabilities, make sure to download the free and comprehensive Specification Sheet and user manual from our website, manualshive.com, to get the most out of this exceptional product.

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Document Number: 001-07160 Rev. *E

Revised June 18, 2008

Page 29 of 29

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.

CY7C1316CV18, CY7C1916CV18
CY7C1318CV18, CY7C1320CV18

© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress. 

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Use may be limited by and subject to the applicable Cypress software license agreement. 

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Document History Page

Document Title: CY7C1316CV18/CY7C1916CV18/CY7C1318CV18/CY7C1320CV18, 18-Mbit DDR-II SRAM 2-Word
Burst Architecture
Document Number: 001-07160

Rev.

ECN No.

Submission 

Date

Orig. of 

Change

Description of Change

**

433284

See ECN

NXR

New data sheet

*A

462615

See ECN

NXR

Changed t

TH 

and t

TL 

from 40 ns to 20 ns, changed t

TMSS

, t

TDIS

, t

CS

, t

TMSH

, t

TDIH

, t

CH 

from

 

10 ns to 5 ns and changed t

TDOV 

from 20 ns to 10 ns in TAP AC Switching 

Characteristics table 
Modified Power-Up waveform

*B

503690

See ECN

VKN

Minor change: Moved data sheet to web

*C

1523383

See ECN

VKN/AESA

Converted from preliminary to final
Updated Logic Block diagram
Removed 300 MHz and 278 MHz speed bins
Added 267 MHz speed bin
Updated I

DD

/I

SB

 specs

Changed DLL minimum operating frequency from 80MHz to 120MHz
Changed t

CYC

 max spec to 8.4ns

Modified footnotes 20 and 28

*D

2507747

See ECN

VKN/PYRS

Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C 
to +125°C” in the “Maximum Ratings“ on page 20
Updated power up sequence waveform and its description
Added footnote #19 related to I

DD

Changed 

Θ

JA 

spec from 28.51 to 18.7; Changed 

Θ

JC 

spec from 5.91 to 4.5

*E

2518624

See ECN

NXR/PYRS

Changed JTAG ID (31:29) from 001 to 000

[+] Feedback 

Summary of Contents for CY7C1316CV18

Page 1: ...ne bit burst counter Addresses for read and write are latched on alternate rising edges of the input K clock Write data is registered on the rising edges of both K and K Read data is driven on the rising edges of C and C if provided or on the rising edge of K and K if C C are not provided Each address location is associated with two 8 bit words in the case of CY7C1316CV18 and two 9 bit words in th...

Page 2: ...Register Read Add Decode Read Data Reg R W Output Logic Reg Reg Reg 8 16 8 NWS 1 0 VREF Write Add Decode 8 20 C C 8 LD Control R W DOFF 1M x 8 Array 1M x 8 Array 8 DQ 7 0 8 CQ CQ Write Reg Write Reg CLK A 19 0 Gen K K Control Logic Address Register Read Add Decode Read Data Reg R W Output Logic Reg Reg Reg 9 18 9 BWS 0 VREF Write Add Decode 9 20 C C 9 LD Control R W DOFF 1M x 9 Array 1M x 9 Array ...

Page 3: ...R W Output Logic Reg Reg Reg 18 36 18 BWS 1 0 VREF Write Add Decode 18 20 C C 18 LD Control Burst Logic A0 A 19 1 R W DOFF 512K x 18 Array 512K x 18 Array 19 18 DQ 17 0 18 CQ CQ Write Reg Write Reg CLK A 18 0 Gen K K Control Logic Address Register Read Add Decode Read Data Reg R W Output Logic Reg Reg Reg 36 72 36 BWS 3 0 VREF Write Add Decode 36 19 C C 36 LD Control Burst Logic A0 A 18 1 R W DOFF...

Page 4: ...Q VSS VSS VSS VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS A A A VSS NC NC NC P NC NC DQ7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1916CV18 2M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 72M A R W NC K NC 144M LD A NC 36M CQ B NC NC NC A NC 288M K BWS0 A NC NC DQ3 C NC NC NC VSS A A A VSS NC NC NC D NC NC NC VSS VSS VSS VSS VSS NC NC NC E NC NC DQ4 VDDQ VSS VSS VSS V...

Page 5: ...C A A NC NC DQ0 R TDO TCK A A A C A A A TMS TDI CY7C1320CV18 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M NC 36M R W BWS2 K BWS1 LD A NC 72M CQ B NC DQ27 DQ18 A BWS3 K BWS0 A NC NC DQ8 C NC NC DQ28 VSS A A0 A VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD V...

Page 6: ...ese address inputs are multiplexed for both read and write operations Internally the device is organized as 2M x 8 2 arrays each of 1M x 8 for CY7C1316CV18 and 2M x 9 2 arrays each of 1M x 9 for CY7C1916CV18 1M x 18 2 arrays each of 512K x 18 for CY7C1318CV18 and 512K x 36 2 arrays each of 256K x 36 for CY7C1320CV18 CY7C1316CV18 Because the least significant bit of the address internally is a 0 on...

Page 7: ...OFF Input DLL Turn Off Active LOW Connecting this pin to ground turns off the DLL inside the device The timing in the DLL turned off operation is different from that listed in this data sheet For normal operation this pin can be connected to a pull up through a 10 KΩ or less pull up resistor The device behaves in DDR I mode when the DLL is turned off In this mode the device can be operated at a fr...

Page 8: ...ck rise the data presented to D 17 0 is latched and stored into the 18 bit write data register provided BWS 1 0 are both asserted active On the subsequent rising edge of the negative input clock K the infor mation presented to D 17 0 is also stored into the write data register provided BWS 1 0 are both asserted active The 36 bits of data are then written into the memory array at the specified loca...

Page 9: ...page 23 DLL These chips use a Delay Lock Loop DLL that is designed to function between 120 MHz and the specified maximum clock frequency During power up when the DOFF is tied HIGH the DLL is locked after 1024 cycles of stable clock The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns However it is not necessary to reset the DLL to lock it to the desired ...

Page 10: ...byte D 8 0 is written into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1316CV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1318CV18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the data portion of a write sequence CY7C1316CV18 only the upper nibble D 7 4 is writte...

Page 11: ...tten into the device D 35 9 remains unaltered L H H H L H During the data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is ...

Page 12: ...he falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a r...

Page 13: ...ndary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE an...

Page 14: ...controller follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR Note 9 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Feedback ...

Page 15: ...ut HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 μA 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 106 0 1 2 Instruction Register Bypass Register Selection Circuitry Selection Circuitry TAP Controller TDI TDO TCK TMS Notes 10 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load ...

Page 16: ... tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 14 Figure 2 TAP Timing and Test Conditions tTL tTH a TDO CL 20 pF Z0 50Ω GND 0 9V 50Ω 1 8V 0V ALL INPUT PULSES 0 9V Test Clock Test Mode Select TCK TM...

Page 17: ... Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z s...

Page 18: ... 3A 90 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C 68 1B 96 2M 13 10M 41 9D 69 3D 97 3P 14 11N 42 11B 70 3C 98 2N 15 9M 43 11C 71 1D 99 2P 16 9N 44 9B 72 2C 100 1P 17 11L 45 10B 73 3E 101 3R 18 11M 46 11A 74 2D 102 4R 19 9L 47 Internal 75 2E 103 4P 20 10L 48 9A 76 1E 104 5P 21 11K 49 8B 77 2F 105 5N 22 1...

Page 19: ...clock K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies down to 120 MHz If the input clock is unstable and the DLL is enabled then the DLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid this provide1024 cycles stable clock t...

Page 20: ...age Note 16 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage VREF 0 1 VDDQ 0 3 V VIL Input LOW Voltage 0 3 VREF 0 1 V IX Input Leakage Current GND VI VDDQ 5 5 μA IOZ Output Leakage Current GND VI VDDQ Out...

Page 21: ...Hz x8 300 mA x9 300 x18 300 x36 320 200 MHz x8 285 mA x9 285 x18 290 x36 300 167 MHz x8 280 mA x9 280 x18 285 x36 295 AC Electrical Characteristics Over the Operating Range 11 Parameter Description Test Conditions Min Typ Max Unit VIH Input HIGH Voltage VREF 0 2 V VIL Input LOW Voltage VREF 0 2 V Electrical Characteristics continued DC Electrical Characteristics Over the Operating Range 12 Paramet...

Page 22: ... Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 18 7 C W ΘJC Thermal Resistance Junction to Case 4 5 C W Figure 4 AC Test Loads and Waveforms 1 25V 0 25V R 50Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES Device RL 50Ω Z0 50Ω VREF 0 75V VREF 0 75V 20 0 75V Under Test 0 75V Device Under Test OUTPUT 0 75V...

Page 23: ...ock Rise LD R W 0 3 0 5 0 6 0 7 ns tSCDDR tIVKH Double Data Rate Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 35 0 4 0 5 ns tSD 23 tDVKH D X 0 Setup to Clock K and K Rise 0 3 0 35 0 4 0 5 ns Hold Times tHA tKHAX Address Hold after K Clock Rise 0 3 0 5 0 6 0 7 ns tHC tKHIX Control Hold after K Clock Rise LD R W 0 3 0 5 0 6 0 7 ns tHCDDR tKHIX Double Data Rate Control Hold after Clock K...

Page 24: ...h Z 25 26 0 45 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 25 26 0 45 0 45 0 45 0 50 ns DLL Timing tKC Var tKC Var Clock Phase Jitter 0 20 0 20 0 20 0 20 ns tKC lock tKC lock DLL Lock Time K C 1024 1024 1024 1024 Cycles tKC Reset tKC Reset K Static to DLL Reset 30 30 30 30 ns Switching Characteristics continued Over the Operating Range 20 21 Cypress Parameter Consortium Parameter Descrip...

Page 25: ...tKHKH tKL tCYC A0 D20 D21 D30 D31 Q00 Q11 Q01 Q10 A1 A2 A3 A4 Q41 tCCQO tCQOH tCCQO tCQOH tKL tCYC K K LD R W A DQ C C CQ CQ SA tKH tKHKH tCQD tCQDOH tCQH tCQHCQH Notes 27 Q00 refers to output from address A0 Q01 refers to output from the next internal burst address following A0 that is A0 1 28 Outputs are disabled High Z one clock cycle after a NOP 29 In this example if address A4 A3 then data Q4...

Page 26: ...Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1916CV18 267BZI CY7C1318CV18 267BZI CY7C1320CV18 267BZI CY7C1316CV18 267BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1916CV18 267BZXI CY7C1318CV18 267BZXI CY7C1320CV18 267BZXI 250 CY7C1316CV18 250BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1916CV18 250BZC CY7C1318C...

Page 27: ...CV18 200BZXI 167 CY7C1316CV18 167BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1916CV18 167BZC CY7C1318CV18 167BZC CY7C1320CV18 167BZC CY7C1316CV18 167BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1916CV18 167BZXC CY7C1318CV18 167BZXC CY7C1320CV18 167BZXC CY7C1316CV18 167BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1...

Page 28: ... A B Ø0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A A 15 00 0 10 13 00 0 10 B C 1 00 5 00 0 36 0 06 0 14 1 40 MAX SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD NOTES PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKA...

Page 29: ...anges without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypr...

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