Cypress Semiconductor CY7C1303BV25 Specification Sheet Download Page 19

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CY7C1306BV25

CY7C1303BV25

Document #: 38-05627 Rev. *A

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Document History Page

Document Title: CY7C1303BV25/CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture
Document Number: 38-05627

REV.

ECN NO.

Issue Date

Orig. of

Change

Description of Change

253010

See ECN

SYT

New Data Sheet

436864

See ECN

NXR

Converted from Preliminary to Final.
Removed 133 MHz & 100 MHz from product offering.
Included the Industrial Operating Range.
Changed C/C Description in the Features Section & Pin Description Table.
Changed t

TCYC

from 100 ns to 50 ns, changed t

from 10 MHz to 20 MHz

and changed t

and t

from 40 ns to 20 ns in TAP AC Switching

Characteristics table
Modified the ZQ pin definition as follows:
Alternately, this pin can be connected directly to V

DDQ

, which enables the

minimum impedance mode
Included Maximum Ratings for Supply Voltage on V

DDQ

Relative to GND

Changed the Maximum Ratings for DC Input Voltage from V

DDQ

to V

DD.

Modified the Description of I

from Input Load current to Input Leakage

Current on page # 15.
Modified test condition in note# 13 from V

DDQ

< V

DDQ

≤

Updated the Ordering Information table and replaced the Package Name
Column with Package Diagram.

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Summary of Contents for CY7C1303BV25

Page 1: ...ts to support Read operations and the Write Port has dedicated Data inputs to support Write operations Access to each port is accomplished through a common address bus The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock QDR has separate data inputs and data outputs to completely eliminate the need to turn around the data bus ...

Page 2: ...18 18 A 18 0 19 18 C C BWS1 Logic Block Diagram CY7C1303BV25 256Kx36 CLK A 17 0 Gen K K Control Logic Address Register D 35 0 Read Add Decode Read Data Reg RPS WPS Q 35 0 Control Logic Address Register Reg Reg Reg 36 18 36 72 Write 36 BWS0 Vref Write Add Decode Data Reg Write Data Reg Memory Array 256Kx36 Memory Array 36 36 A 17 0 18 36 C C BWS1 BWS2 BWS3 Logic Block Diagram CY7C1306BV25 Selection...

Page 3: ...D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1306BV25 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A NC Gnd 288M NC 72M WPS BWS2 K BWS1 RPS NC 36M Gnd 144M NC B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A A A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q...

Page 4: ...d operations or K and K when in single clock mode When the Read port is deselected Q x 0 are automatically three stated CY7C1303BV25 Q 17 0 CY7C1306BV25 Q 35 0 RPS Input Synchronous Read Port Select active LOW Sampled on the rising edge of positive input clock K When active a Read operation is initiated Deasserting will cause the Read port to be deselected When deselected the pending access is all...

Page 5: ...e positive output clock C This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the same K clock rise the data presented to D 17 0 is latched and stored into the lower 18 bit Write Data register provided BWS ...

Page 6: ...e SRAM and VSS to allow the SRAM to adjust its output driver impedance The value of RQ must be 5X the value of the intended line impedance driven by the SRAM The allowable range of RQ to guarantee impedance matching with a tolerance of 15 is between 175Ω and 350Ω with VDDQ 1 5V The output impedance is adjusted every 1024 cycles to account for drifts in supply voltage and temperature Application Ex...

Page 7: ...ower byte D 8 0 is written into the device D 35 9 will remain unaltered L H H H L H During the Data portion of a Write sequence only the lower byte D 8 0 is written into the device D 35 9 will remain unaltered H L H H L H During the Data portion of a Write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 will remain unaltered H L H H L H During the Data portion of a Write...

Page 8: ...etween the TDI and TDO pins as shown in TAP Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow...

Page 9: ...he TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS in...

Page 10: ...to each state represents the value at TMS at the rising edge of TCK TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR SCAN CAPTURE DR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 Feedback ...

Page 11: ...Hz tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns Set up Times tTMSS TMS Set up to TCK Clock Rise 10 ns tTDIS TDI Set up to TCK clock Rise 10 ns tCS Capture Set up to TCK Rise 10 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns Notes 10 These characteristic pertain to the TAP inputs TMS TCK TDI and TDO Parallel ...

Page 12: ...ck Test Mode Select TCK TMS Test Data In TDI Test Data Out TDO tTCYC tTMSH tTL tTH tTMSS tTDIS tTDIH tTDOX tTDOV 50Ω 2 5V 0V ALL INPUT PULSES 1 25V Identification Register Definitions Instruction Field Value Description CY7C1303BV25 CY7C1306BV25 Revision Number 31 29 000 000 Version number Cypress Device ID 28 12 01011010010010101 01011010010100101 Defines the type of SRAM Cypress JEDEC ID 11 1 00...

Page 13: ...Z 010 Captures the Input Output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the Input Output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction...

Page 14: ... 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 16 9N 43 11C 70 3C 97 3P 17 11L 44 9B 71 1D 98 2N 18 11M 45 10B 72 2C 99 2P 19 9L 46 11A 73 3E 100 1P 20 10L 47 Internal 74 2D 101 3R 21 11K 48 9A 75 2E 102 4R 22 10K 49 8B 76 1E 103 ...

Page 15: ... 0 75V 0 68 0 75 0 95 V IX Input Leakage Current GND VI VDDQ 5 5 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply VDD Max IOUT 0 mA f fMAX 1 tCYC 500 mA ISB1 Automatic Power Down Current Max VDD Both Ports Deselected VIN VIH or VIN VIL f fMAX 1 tCYC Inputs Static 240 mA AC Input Requirements Over the Operating Range Parameter Description Test Conditions Min...

Page 16: ...fter Clock K and K Rise 0 7 ns tHC tHC Control Signals Hold after Clock K and K Rise RPS WPS BWS0 BWS1 0 7 ns tHD tHD D x 0 Hold after Clock K and K Rise 0 7 ns Output Times tCO tCHQV C C Clock Rise or K K in single clock mode to Data Valid 2 5 ns tDOH tCHQX Data Output Hold after Output C C Clock Rise Active to Active 1 2 ns tCHZ tCHZ Clock C and C rise to High Z Active to High Z 23 24 2 5 ns tCL...

Page 17: ...wing A0 i e A0 1 26 Outputs are disabled High Z one clock cycle after a NOP 27 In this example if address A2 A1 then data Q2 0 D10 and Q21 D11 Write data is forwarded immediately as read results This note applies to the whole diagram READ READ WRITE WRITE WRITE NOP READ WRITE NOP K 1 2 3 4 5 8 10 6 7 K RPS WPS A Q D C C A1 A0 D10 tKH tKHKH tKHCH tCO tKL tCYC tHC tSA tHA tHD tKHCH DON T CARE UNDEFI...

Page 18: ...d MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1303BV25 167BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1306BV25 167BZC CY7C1303BV25 167BZXC 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead free CY7C1306BV25 167BZXC CY7C1303BV25 167BZI 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1306BV25 167BZI CY7C1303B...

Page 19: ...scription Table Changed tTCYC from 100 ns to 50 ns changed tTF from 10 MHz to 20 MHz and changed tTH and tTL from 40 ns to 20 ns in TAP AC Switching Characteristics table Modified the ZQ pin definition as follows Alternately this pin can be connected directly to VDDQ which enables the minimum impedance mode Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Rat...

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