Cypress Semiconductor CY7C1298H Specification Sheet Download Page 12

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CY7C1298H

Document #: 38-05665 Rev. *B

Page 12 of 16

Write Timing

[16, 17]

Note:

17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW

[A:B]

LOW.

Switching Waveforms

(continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

[A:B]

ADV

BURST READ

BURST WRITE

D(A2)

D(A2 + 1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

OEHZ

tADVH

tADVS

tWEH

tWES

tWEH

tWES

Byte write signals are ignored for first cycle when
ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE

UNDEFINED

D(A1)

High-Z

Data in (D)

Data Out (Q)

[+] Feedback

Summary of Contents for CY7C1298H

Page 1: ...rst Control inputs ADSC ADSP and ADV Write Enables BW A B and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV Addre...

Page 2: ...R Q1 Q0 ADSC BWB BWA CE1 DQB DQPB BYTE WRITEREGISTER DQA DQPA BYTE WRITEREGISTER ENABLE REGISTER OE SENSE AMPS MEMORY ARRAY ADSP 2 A 1 0 MODE CE2 CE3 GW BWE PIPELINED ENABLE DQs DQPA DQPB OUTPUT REGISTERS INPUT REGISTERS E OUTPUT BUFFERS DQB DQPB BYTE WRITEDRIVER DQA DQPA BYTE WRITEDRIVER SLEEP CONTROL ZZ A0 A1 A Feedback ...

Page 3: ...QPB NC VSSQ VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1...

Page 4: ... state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK active LOW When asserted it automatically increments the address in a burst cycle ADSP Input Synchronous Address Strobe from Processor sampled on the rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers A 1 0 are also loaded into the burst counter W...

Page 5: ...e the data presented to the DQx inputs is written into the corre sponding address location in the memory core If GW is HIGH then the write operation is controlled by BWE and BW A B signals The CY7C1298H provides byte write capability that is described in the Write Cycle Description table Asserting the Byte Write Enable input BWE with the selected Byte Write input will selectively write to only the...

Page 6: ...st Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H X X L X H H H L L H Q Read Cycle Sus...

Page 7: ...tes H L L L Write all bytes L X X X ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ VDD 0 2V 40 mA tZZS Device operation to ZZ ZZ VDD 0 2V 2tCYC ns tZZREC ZZ recovery time ZZ 0 2V 2tCYC ns tZZI ZZ Active to Sleep current This parameter is sampled 2tCYC ns tRZZI ZZ inactive to exit Sleep current This parameter is sampled 0 ns...

Page 8: ...or 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 7 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply Current VDD Max IOUT ...

Page 9: ...follow standard test methodsandproceduresformeasuring thermal impedance per EIA JESD51 30 32 C W ΘJC Thermal Resistance Junction to case 6 85 C W AC Test Loads and Waveforms Note 9 Tested initially and after any design or process change that may affect these parameters OUTPUT R 317Ω R 351Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL 50Ω Z0 50Ω VT 1 5V 3 3V ALL INPUT PULSES VDDQ GND 90 10 90 10 1 ns...

Page 10: ...ise 0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns tWEH GW BWE BW A B Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Chip Enable Hold After CLK Rise 0 5 0 5 ns Notes 10 This part has a voltage regulator internally tpower is the time that the power needs to be supplied above VDD minimum initially before a read or ...

Page 11: ...3 is HIGH tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES GW BWE BW Data Out Q High Z tDOH tCO ADV tOEHZ tCO Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its initial state tADVH tADVS tWEH tWES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A3 Q A2 3 A2 A3 Deselect cycle Burst continued with new base address ADV suspends burst DON T CARE UNDEFINED A B CLZ t...

Page 12: ...S ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE BW A B ADV BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS tWEH tWES t DH t DS GW tWEH tWES Byte write signals are ignored for first cycle when ADSP initiates burst ADSC extends burst ADV suspends burst DON T CARE UNDEFINED D A1 High Z Data in ...

Page 13: ...y ADSP or ADSP 19 GW is HIGH Switching Waveforms continued tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6 Data In D BURST READ Back to Back READs High Z Q A2 Q A1 Q A4 Q A4 1 Q A4 2 tWEH tWES Q A4 3 tOEHZ tDH tDS tOELZ tCLZ tCO Back to Back WRITEs A1 BWE BW A B A3 DON T CARE UNDEFINED Feedback ...

Page 14: ...ed when entering ZZ mode See truth table for all possible signal conditions to deselect the device 21 I Os are in High Z when exiting ZZ sleep mode Switching Waveforms continued tZZ I SUPPLY CLK ZZ tZZREC ALL INPUTS except ZZ DON T CARE I DDZZ tZZI tRZZI Outputs Q High Z DESELECT or READ Only Feedback ...

Page 15: ...gistered trademark of IBM All product and company names mentioned in this document are the trademarks of their respective holders Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed MHz Ordering Code Package Diagram Package Type Operating Range 100 CY7C1298H ...

Page 16: ...Corporation on Page 1 from 3901 North First Street to 198 Champion Court Added 2 5VI O option Changed Three State to Tri State Included Maximum Ratings for VDDQ relative to GND Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Modified test condition from VIH VDD to VIH VDD Replaced Package Name column with Package Diagram in the Ordering Infor...

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