Cypress Semiconductor CY7C1161V18 Specification Sheet Download Page 23

Page: 23 / 29

CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18

Document Number: 001-06582 Rev. *D

Page 23 of 29

Switching Characteristics

Over the operating range

[23, 24]

Cypress

Parameter

Consortium

Parameter

Description

400 MHz

375 MHz

333 MHz

300 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

POWER

(Typical) to the First Access

[25]

–

CYC

KHKH

K Clock Cycle Time

2.50 8.40 2.66 8.40

3.0

8.40

3.3

8.40

KHKL

Input Clock (K/K) HIGH

0.4

–

0.4

–

0.4

–

0.4

–

CYC

KLKH

Input Clock (K/K) LOW

0.4

–

0.4

–

0.4

–

0.4

–

CYC

KHKH

K Clock Rise to K Clock Rise
(rising edge to rising edge)

1.06

–

1.13

–

1.28

–

1.40

–

Setup Times

AVKH

Address Setup to K Clock Rise

0.4

–

0.4

–

0.4

–

0.4

–

IVKH

Control Setup to K Clock Rise (RPS, WPS)

0.4

–

0.4

–

0.4

–

0.4

–

SCDDR

IVKH

Double Data Rate Control Setup to Clock (K, K)
Rise (BWS

, BWS

BWS

, BWS

)

0.28

–

0.28

–

0.28

–

0.28

–

DVKH

[X:0]

Setup to Clock (K/K) Rise

0.28

–

0.28

–

0.28

–

0.28

–

Hold Times

KHAX

Address Hold after K Clock Rise

0.4

–

0.4

–

0.4

–

0.4

–

KHIX

Control Hold after K Clock Rise (RPS, WPS)

0.4

–

0.4

–

0.4

–

0.4

–

HCDDR

KHIX

Double Data Rate Control Hold after Clock (K/K)
Rise (BWS

, BWS

BWS

, BWS

)

0.28

–

0.28

–

0.28

–

0.28

–

KHDX

[X:0]

Hold after Clock (K/K) Rise

0.28

–

0.28

–

0.28

–

0.28

–

Output Times

CHQV

K/K Clock Rise to Data Valid

–

0.45

–

0.45

–

0.45

–

0.45

DOH

CHQX

Data Output Hold after Output K/K Clock Rise
(Active to Active)

–0.45

–

–0.45

–

–0.45

–

–0.45

–

CCQO

CHCQV

K/K Clock Rise to Echo Clock Valid

–

0.45

–

0.45

–

0.45

–

0.45

CQOH

CHCQX

Echo Clock Hold after K/K Clock Rise

–0.45

–

–0.45

–

–0.45

–

–0.45

–

CQD

CQHQV

Echo Clock High to Data Valid

–

0.2

CQDOH

CQHQX

Echo Clock High to Data Invalid

–0.2

–

–0.2

–

–0.2

–

–0.2

–

CQH

CQHCQL

Output Clock (CQ/CQ) HIGH

[26]

0.81

–

0.88

–

1.03

–

1.15

–

CQHCQH

CQ Clock Rise to CQ Clock Rise

[26]

(rising edge to rising edge)

0.81

–

0.88

–

1.03

–

1.15

–

CHZ

CHQZ

Clock (K/K) Rise to High Z (Active to High Z)

[27, 28]

–

0.45

–

0.45

–

0.45

–

0.45

CLZ

CHQX1

Clock (K/K) Rise to Low Z

[27, 28]

–0.45

–

–0.45

–

–0.45

–

–0.45

–

QVLD

Echo Clock High to QVLD Valid

[29]

–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20

Notes

24. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being

operated and outputs data with the output timings of that frequency range.

25. This part has a voltage regulator internally; t

POWER

is the time that the power needs to be supplied above V

minimum initially before a Read or Write operation can

be initiated.

26. These parameters are extrapolated from the input timing parameters (t

KHKH

– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t

KC Var

) is already

included in the t

KHKH

). These parameters are only guaranteed by design and are not tested in production.

27. t

CHZ

, t

CLZ

are specified with a load capacitance of 5 pF as in part (b) of

AC Test Loads and Waveforms

. Transition is measured

100 mV from steady state voltage.

28. At any voltage and temperature t

CHZ

is less than t

CLZ

and t

CHZ

less than t

29. t

QVLD

spec is applicable for both rising and falling edges of QVLD signal.

[+] Feedback

Summary of Contents for CY7C1161V18

Page 1: ...arate ports to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus that is required with common IO devices Each port can be accessed through a common address bus Ad...

Page 2: ... Reg Reg Reg 16 19 8 32 8 NWS 1 0 VREF Write Add Decode Write Reg 16 A 18 0 19 512K x 8 Array 512K x 8 Array 512K x 8 Array Write Reg Write Reg Write Reg 8 CQ CQ DOFF QVLD 512K x 9 Array CLK A 18 0 Gen K K Control Logic Address Register D 8 0 Read Add Decode Read Data Reg RPS WPS Q 8 0 Control Logic Address Register Reg Reg Reg 18 19 9 36 9 BWS 0 VREF Write Add Decode Write Reg 18 A 18 0 19 512K x...

Page 3: ... Reg 36 18 18 72 18 BWS 1 0 VREF Write Add Decode Write Reg 36 A 17 0 18 256K x 18 Array 256K x 18 Array 256K x 18 Array Write Reg Write Reg Write Reg 18 CQ CQ DOFF QVLD 128K x 36 Array CLK A 16 0 Gen K K Control Logic Address Register D 35 0 Read Add Decode Read Data Reg RPS WPS Q 35 0 Control Logic Address Register Reg Reg Reg 72 17 36 144 36 BWS 3 0 VREF Write Add Decode Write Reg 72 A 16 0 17 ...

Page 4: ...NC VSS NC Q2 NC NC NC VREF NC NC VDDQ NC VDDQ NC NC VDDQ VDDQ VDDQ D1 VDDQ NC Q1 NC VDDQ VDDQ NC VSS NC D0 NC TDI TMS VSS A NC A NC D2 NC ZQ NC Q0 NC NC NC NC A NC 144M CY7C1176V18 2M x 9 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC 72M A NC K WPS NC 144M NC NC NC NC NC TDO NC NC D6 NC NC NC TCK NC NC A NC 288M K BWS0 VSS A NC A NC VSS VSS VSS VSS VDD A VSS VSS VSS VDD Q...

Page 5: ...D5 NC NC VREF NC Q3 VDDQ NC VDDQ NC Q5 VDDQ VDDQ VDDQ D4 VDDQ NC Q4 NC VDDQ VDDQ NC VSS NC D2 NC TDI TMS VSS A NC A D7 D6 NC ZQ D3 Q2 D1 Q1 D0 NC A NC CY7C1165V18 512K x 36 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R A CQ Q27 D27 D28 D34 DOFF Q33 NC 288M NC 72M BWS2 K WPS BWS1 Q18 D18 Q30 D31 D33 TDO Q28 D29 D22 D32 Q34 Q31 TCK D35 D19 A BWS3 K BWS0 VSS A NC A Q19 VSS VSS VSS VSS VDD A VSS VSS VSS...

Page 6: ... and write operations Internally the device is organized as 2M x 8 4 arrays each of 512K x 8 for CY7C1161V18 2M x 9 4 arrays each of 512K x 9 for CY7C1176V18 1M x 18 4 arrays each of 256K x 18 for CY7C1163V18 and 512K x 36 4 arrays each of 128K x 36 for CY7C1165V18 Therefore only 19 address inputs are needed to access the entire memory array of CY7C1161V18 and CY7C1176V18 18 address inputs for CY7...

Page 7: ...sheet For normal operation this pin is connected to a pull up through a 10 KΩ or less pull up resistor The device behaves in QDR I mode when the DLL is turned off In this mode the device operates at a frequency of up to 167 MHz with QDR I timing TDO Output TDO for JTAG TCK Input TCK Pin for JTAG TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N A Not Connected to the Die Can be tied to an...

Page 8: ... the next rising edge of the negative input clock K This allows for a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the following K clock rise the data presented to D 17 0 is latched and stored into the lower 18 bit write ...

Page 9: ...are generated by the QDR II CQ is referenced with respect to K and CQ is refer enced with respect to K These are free running clocks and are synchronized to the input clock of the QDR II The timings for the echo clocks are shown in the AC timing table Valid Data Indicator QVLD QVLD is provided on the QDR II to simplify data capture on high speed systems The QVLD is generated by the QDR II device a...

Page 10: ...K RPS WPS BWS D A K SRAM 1 RQ 250ohms ZQ CQ CQ Q K RPS WPS BWS RPS WPS BWS R 50ohms Vt V 2 DDQ R Notes 2 The above application shows four QDR II being used 3 X Don t Care H Logic HIGH L Logic LOW represents rising edge 4 Device powers up deselected and the outputs in a tri state condition 5 A represents address location latched by the devices when transaction was initiated A 1 A 2 and A 3 represen...

Page 11: ...ence CY7C1161V18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1163V18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the data portion of a write sequence CY7C1161V18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1163V18 only the upper byte D 17 9 is written into the device D 8 0...

Page 12: ... is written into the device D 8 0 and D 35 18 remains unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H H L H L H During the data portion of a write sequence only the byte D 26 18 is written into the device D 17 0 and D 35 27 remains unaltered H H L H L H During the data portion of a write sequenc...

Page 13: ...n the falling edge of TCK Instruction Register Three bit instructions are serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 16 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a r...

Page 14: ...ry scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for th...

Page 15: ...agram 12 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 Note 12 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Feedback Feedback ...

Page 16: ... LOW Voltage IOL 100 μA 0 2 V VIH Input HIGH Voltage 0 65 VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35 VDD V IX Input and Output Load Current GND VI VDD 5 5 μA 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 106 0 1 2 Instruction Register Bypass Register Selection Circuitry Selection Circuitry TAP Controller TDI TDO TCK TMS Notes 13 These characteristic pertain to the TAP inp...

Page 17: ...Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions The Tap Timing and Test Conditions for the CY7C1161V18 CY7C1176V18 CY7C1163V18 and CY7C1165V18 follows 17 tTL tTH a TDO CL 20 pF Z0 50Ω GND 0 9V 50Ω 1 8V 0V ALL INPUT PULSES 0 9V Test Clock T...

Page 18: ... Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO This forces all SRAM output drivers to a High Z state RESERVED...

Page 19: ... 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 16 9N 43 11C 70 3C 97 3P 17 11L 44 9B 71 1D 98 2N 18 11M 45 10B 72 2C 99 2P 19 9L 46 11A 73 3E 100 1P 20 10L 47 Internal 74 2D 101 3R 21 11K 48 9A 75 2E 102 4R 22 10K 49 8B...

Page 20: ...able power and clock K K for 2048 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies down to 120 MHz If the input clock is unstable and the DLL is enabled then the DLL locks onto an incorrect frequency causing unstable SRAM behavior To avoid this provide 2048 cycles s...

Page 21: ...mpedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage VREF 0 1 VDDQ 0 15 V VIL Input LOW Voltage 0 15 VREF 0 1 V IX Input Leakage Current GND VI VDDQ 2 2 μA IOZ Output Leakage Current GND VI VDDQ Output Disabled 2 2 μA VREF Input Reference Voltage 21 Typical Value 0 75V 0 68 0 75 0 95 V IDD 22 VDD Operating Supply VDD Max IOUT 0 mA f fmax...

Page 22: ...t Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 17 2 C W ΘJC Thermal Resistance junction to case 4 15 C W AC Test Loads and Waveforms Figure 5 AC Test Loads and Waveforms 1 25V 0 25V R 50Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES Device RL 50Ω Z0 50Ω VREF 0 75V VREF 0 75V 23 0 75V Under Test 0 75V Device Under Test OU...

Page 23: ...0 45 0 45 ns tCQOH tCHCQX Echo Clock Hold after K K Clock Rise 0 45 0 45 0 45 0 45 ns tCQD tCQHQV Echo Clock High to Data Valid 0 2 0 2 0 2 0 2 ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 2 0 2 0 2 0 2 ns tCQH tCQHCQL Output Clock CQ CQ HIGH 26 0 81 0 88 1 03 1 15 ns tCQHCQH tCQHCQH CQ Clock Rise to CQ Clock Rise 26 rising edge to rising edge 0 81 0 88 1 03 1 15 ns tCHZ tCHQZ Clock K K Rise...

Page 24: ...20 ns tKC lock tKC lock DLL Lock Time K 2048 2048 2048 2048 Cycles tKC Reset tKC Reset K Static to DLL Reset 30 30 30 30 30 ns Switching Characteristics Over the operating range 23 24 continued Cypress Parameter Consortium Parameter Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Min Max Min Max Min Max Min Max Note 30 Hold to VIH or VIL Feedback Feedback ...

Page 25: ...TE 1 2 3 4 5 6 7 8 CQ CQ Q tCQOH CCQO t CLZ t t CO tDOH tCQDOH CQD t tCHZ tCQOH CCQO t tQVLD QVLD QVLD DON T CARE UNDEFINED Read Latency 2 5 Cycles Q00 Q01 Q20 Q02 Q21 Q03 Q22 Q23 tCQH tCQHCQH Notes 31 Q00 refers to output from address A0 Q01 refers to output from the next internal burst address following A0 i e A0 1 32 Outputs are disabled High Z one clock cycle after a NOP 33 In this example if ...

Page 26: ...l Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1176V18 400BZI CY7C1163V18 400BZI CY7C1165V18 400BZI CY7C1161V18 400BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1176V18 400BZXI CY7C1163V18 400BZXI CY7C1165V18 400BZXI 375 CY7C1161V18 375BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1176V18 375BZC CY7C1163V18 375BZC CY...

Page 27: ...8 333BZXI 300 CY7C1161V18 300BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1176V18 300BZC CY7C1163V18 300BZC CY7C1165V18 300BZC CY7C1161V18 300BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1176V18 300BZXC CY7C1163V18 300BZXC CY7C1165V18 300BZXC CY7C1161V18 300BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Indust...

Page 28: ...0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A A 15 00 0 10 13 00 0 10 B C 1 00 5 00 0 36 0 06 0 14 1 40 MAX SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD NOTES PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE COD...

Page 29: ...LITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonabl...

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