CY62148ESL MoBL
®
Document #: 001-50045 Rev. **
Page 6 of 10
Switching Characteristics
Over the Operating Range
[9]
Parameter
Description
55 ns
Unit
Min
Max
Read Cycle
t
RC
Read Cycle Time
55
ns
t
AA
Address to Data Valid
55
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE LOW to Data Valid
55
ns
t
DOE
OE LOW to Data Valid
25
ns
t
LZOE
OE LOW to Low Z
[10]
5
ns
t
HZOE
OE HIGH to High Z
[10, 11]
20
ns
t
LZCE
CE LOW to Low Z
[10]
10
ns
t
HZCE
CE HIGH to High Z
[10, 11]
20
ns
t
PU
CE LOW to Power Up
0
ns
t
PD
CE HIGH to Power Up
55
ns
Write Cycle
[12]
t
WC
Write Cycle Time
55
ns
t
SCE
CE LOW to Write End
40
ns
t
AW
Address Setup to Write End
40
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Setup to Write Start
0
ns
t
PWE
WE Pulse Width
40
ns
t
SD
Data Setup to Write End
25
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High Z
[10, 11]
20
ns
t
LZWE
WE HIGH to Low Z
[10]
10
ns
Notes
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in
AC Test Loads and Waveforms
on page 4.
10. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
11. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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