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CY2291

Document #: 38-07189 Rev. *C

Page 2 of 12

Pinouts

Figure 1.  CY2291- 20-pin SOIC 

Pin Definitions

Name

Pin Number 

Description

32XOUT

1

32.768-kHz crystal feedback.

32K

2

32.768-kHz output (always active if VBATT is present).

CLKC

3

Configurable clock output C.

VDD

4, 16

Voltage supply.

GND

5

Ground.

XTALIN

[1]

6

Reference crystal input or external reference clock input.

XTALOUT

[1, 2]

7

Reference crystal feedback.

XBUF

8

Buffered reference clock output.

CLKD

9

Configurable clock output D.

CPUCLK

10

CPU frequency clock output.

CLKB

11

Configurable clock output B.

CLKA

12

Configurable clock output A.

CLKF

13

Configurable clock output F.

S0

14

CPU clock select input, bit 0.

S1

15

CPU clock select input, bit 1.

S2/SUSPEND

17

CPU clock select input, bit 2. Optionally enables suspend feature when LOW.

[3]

SHUTDOWN/OE

18

Places outputs in three-state

[4]

 condition and shuts down chip when LOW. Optionally, only 

places outputs in three-state

[4]

 condition and does not shut down chip when LOW.

VBATT

19

Battery supply for 32.768-kHz circuit.

32XIN

20

32.768-kHz crystal input.

CLKB

1

2

3

4

5

6

7

8

9

10

11

12

13

14

32XOUT

32K

CLKC

VDD

GND

XTALIN

XTALOUT

XBUF

32XIN

VBATT

SHUTDOWN/OE

S2/SUSPEND

VDD
S1

S0

CLKF

15

16

17

18

19

20

CLKD

CPUCLK

CLKA

Notes

1. For best accuracy, use a parallel-resonant crystal, C

LOAD

 

 17 pF or 18 pF.

2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information.
4. The CY2291 has weak pull downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.

[+] Feedback 

Summary of Contents for CY2291

Page 1: ...d on CPUCLK output Enables application compatibility Industry standard packaging saves on board space Part Number Outputs Input Frequency Range Output Frequency Range Specifics CY2291 8 10 MHz 25 MHz...

Page 2: ...select input bit 2 Optionally enables suspend feature when LOW 3 SHUTDOWN OE 18 Places outputs in three state 4 condition and shuts down chip when LOW Optionally only places outputs in three state 4...

Page 3: ...izable set of outputs and or PLLs when LOW All PLLs and any of the outputs except 32K can be shut off in nearly any combination The only limitation is that if a PLL is shut off all outputs derived fro...

Page 4: ...8 kHz HIGH Level Output Voltage IOH 0 5 mA VBATT 0 5 V VOL 32 32 768 kHz LOW Level Output Voltage IOL 0 5 mA 0 4 V VIH HIGH Level Input Voltage 9 Except crystal pins 2 0 V VIL LOW Level Input Voltage...

Page 5: ...0V Parameter Description Conditions Min Typ Max Unit VOH HIGH Level Output Voltage IOH 4 0 mA 2 4 V VOL LOW Level Output Voltage IOL 4 0 mA 0 4 V VOH 32 32 768 kHz HIGH Level Output Voltage IOH 0 5 mA...

Page 6: ...to enter three state mode after SHUTDOWN OE goes LOW 10 15 ns t6 Output Enable Time Time for output to leave three state mode after SHUTDOWN OE goes HIGH 10 15 ns t7 Skew Skew delay between any ident...

Page 7: ...fter SHUTDOWN OE goes LOW 10 15 ns t6 Output Enable Time Time for output to leave three state mode after SHUTDOWN OE goes HIGH 10 15 ns t7 Skew Skew delay between any identical or related outputs 3 12...

Page 8: ...o peak period jitter t9A Max t9A min of clock period fOUT 4 MHz 0 5 1 t9B Clock Jitter 14 Peak to peak period jitter t9B Max t9B min 4 MHz fOUT 16 MHz 0 7 1 ns t9C Clock Jitter 14 Peak to peak period...

Page 9: ...C Clock Jitter 14 Peak to peak period jitter 16 MHz fOUT 50 MHz 400 500 ps t9D Clock Jitter 14 Peak to peak period jitter fOUT 50 MHz 250 350 ps t10A Lock Time for CPLL Lock Time from Power Up 25 50 m...

Page 10: ...Pb Free CY2291SXC XXX 20 Pin SOIC Commercial 5 0V CY2291SXC XXXT 20 Pin SOIC Tape and Reel Commercial 5 0V CY2291SXL XXX 20 Pin SOIC Commercial 3 3V CY2291SXL XXXT 20 Pin SOIC Tape and Reel Commercia...

Page 11: ...CY2291 Document 38 07189 Rev C Page 11 of 12 Package Diagram Figure 6 20 Pin 300 MIL SOIC Package Outline 51 85024 C Feedback...

Page 12: ...R IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without fu...

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