CYPRES WICED CYW920706WCDEVAL, Hardware User'S Manual

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Interface Signal Function Selection Restrictions and Considerations
CYW920706WCDEVAL Hardware User Guide Doc. No.: 002-16535 Rev. ** 34
Option
PUART_RX PUART_TX PUART_RTS PUART_CTS
Pin LHL GPIO Pxx Pin
LHL GPIO
Pxx
Pin
LHL GPIO
Pxx
Pin
LHL GPIO
Pxx
32 F7 P25 G8 P24 C6 P30 A8 P35
33 F7 P25 G8 P24 D6 P6 A8 P3
34 F7 P25 G8 P24 D6 P6 A8 P35
Table 9-4. CYW20706 PUART Bus-Configuration Options When PUART_RX Is on the Upper Pad Bank
PUART bus-configuration options presented in Table 9-4 will be further reduced by the selected SPI1 bus-configuration option.
For example, SPI1 master bus-configuration option 2 (from Table 9-2 ) requires digital I/O pins G8, F8, and F7. Therefore, all
PUART bus-configuration options (in Table 9-4 ) that use G8, F8, or F7 cannot be used if SPI1 master bus-configuration option
2 is used. So the remaining PUART bus-configuration options become 1–6, 15, and 16.
9.5 Broadcom Serial Control (BSC) (Compatible with I
2
C)
CYW20706 supports a Broadcom Serial Control (BSC) interface.
Note: BSC is a proprietary Cypress interface that is compatible with I
2
C.
The following information applies to the BSC interface:

There are three possible choices for the mapping of BSC signals (SDA and SCL) to CYW20706 pins as shown in the table
below. The parameter used for the
wiced_hal_i2c_init function call for each selection of pins is also provided.
SDA SCL Configuration Parameter Name
(Pin C7)
I2S_DIN/PCM_IN/SDA
1
(Pin A8)
I2S_DOUT/PCM_OUT/SCL
1
WICED_I2C_SDA_I2S_DOUT_PCM_OUT_SCL_I2S_DIN_PCM_IN
(Pin A8) P35 (Pin B7) P37 WICED_I2C_SDA_P35_SCL_P37
(Pin E8) SFLASH_MOSI
2
(Pin D8) SFLASH_MISO
2
WICED_I2C_SDA_SFLASH_MOSI_SCL_SFLASH_MISO
Table 9-5. BSC Signals Pins and Parameters

The interface supports the following transfer types:

Read

Write

Combined write then read
Note: The BSC block generates a repeated START condition between the two parts of a combined transfer.

The maximum transaction length is 64 bytes.

Both low-speed and fast-mode slaves are supported at a maximum clock speed of 4000 kbps. The maximum clock speed
is 2400 kbps for slaves that use clock-cycle stretching.
Note: Clock speeds may be less than the speeds indicated above (for example, if an external pull-up resistor is used and
it affects transmission time).

Multi-master bus mode is not supported and, thus, CYW20706 must be the only bus master.

Only 7-bit slave addresses are supported.

Information on the API functions that support the interface is in wiced_hal_i2c.h .
1
These pins have a 4.7K pull up on the CYW920706WCDEVAL kit.
2
These pins cannot be used for BSC by default on the CYW920706CDEVAL kit because they are used for SPI communication with the
serial flash.