CyberResearch
®
Serial Communication
COMHP 101
CyberResearch, Inc
.
3
25 Business Park Drive
P: (203) 483-8815; F: (203) 483-9024
Branford, CT USA
www.cyberresearch.com
Technical Description
The
COMHP 101
adapter was designed for seamless integration into any PCI based system. The
COMHP 101
adapter requires a PCI slot, one IRQ, an 8 byte block of I/O address and a 16K block or 256K block of memory
address. The memory range of this adapter can be configured to reside in the lower 1 Megabyte memory only or
anywhere in upper memory. Low memory must to be configured as 16 X 16K blocks of page memory. High
memory can be configured as a 256K linear block or 16K paged memory.
Features
•
Single channel high speed sync/async wide area network (WAN) interface
•
RS-232, RS-422/449, EIA-530, V.35 and RS-485 serial interface capability with versatile cabling options
•
Multi-protocol capable including: PPP (point-to-point protocol), Frame Relay, X.25, high-speed Async,
Bi-Sync, Mono-Sync, HDLC, SDLC, etc.
•
Ideal for T1, Fractional T1, E1, and ISDN and other WAN applications
•
On-board Z16C32 (IUSC™) with built in DMA controller and 32 byte FIFO buffer
•
Up to 10 Mbps burst mode
•
256K of on-board RAM
•
Link list DMA supported
•
16-bit data path
•
OEM Security feature available as an option
IUSC™
The
COMHP 101
is based on a single Zilog Z16C32 IUSC (
I
ntegrated
U
niversal
S
erial
C
ontroller). Application
and driver software access the IUSC registers through the first 256 bytes of on-board RAM. Register access to the
IUSC can be disabled via I/O registers allowing the first 256 bytes of RAM to be used for buffer storage. The IUSC
has a built-in DMA controller that allows high-speed data transfers directly to and from the 256K block of on-board
memory. The IUSC’s built-in DMA controller supports 4 different modes of DMA transfer: Single Buffer,
Pipelined, Array, and Link List. An on-board 20MHz oscillator clocks the IUSC.
RAM
The memory window is located by BIOS PCI setup or the Set PCI function. The window size is a 16K paged or
256K linear block. In paged mode the registers are located in the I/O registers.
•
Low Memory options: 16 pages of 16K memory blocks totaling 256K.
•
High Memory options: 16 pages of 16K memory blocks totaling 256K or one linear block of 256K
memory.
