SCRAMNET OVERVIEW
Copyright 2007
2-7
S SC150e HARDWARE REFERENCE
INCOMING INTERRUPT
Figure 2-4 demonstrates the process of receiving a message with the interrupt bit set. The
data is written to shared memory and the address is placed in CSR5 and CSR4 to await
being sent to the host. If the Receive Interrupt Enable ACR[0], Host Interrupt Enable
CSR0[3], and the Interrupt Memory Mask Match Enable CSR0[5] are set, and network
interrupt data is received for any one of the selected interrupt memory locations the
following occurs:
•
The data is stored in that location
•
The S SC150e address of the memory location is placed on the
Interrupt FIFO queue, and
•
An interrupt is sent to the processor.
NETWORK ERRORS
The Interrupt on (Network) Errors mode is enabled by setting CSR0[7] ON. Network
errors are defined in CSR1 according to an interrupt mask set in CSR9. When an
incoming foreign message generates an interrupt, there is no way to mask the interrupt
according to the content of the message. However, specific error conditions are identified.
CPU
ACR
SHARED MEMORY
Address
Data
Interrupt Bit
RING
NETWORK
LOGIC
RING
Address
Data
OUTGOING
A22 - A0
D31 - D0
TIE
D31 - D0
A22 - A0
D31 - D0
1
Figure 2-3 Outgoing Interrupt
Summary of Contents for SCRAMNet+ SC150e
Page 2: ......
Page 79: ...OPERATION Copyright 2007 5 29 SCRAMNet SC150e HARDWARE REFERENCE Figure 5 10 Quad Switch ...
Page 82: ......
Page 94: ......
Page 108: ......
Page 121: ...D D CONFIGURATION AIDS APPENDIX D CONFIGURATION AIDS ...
Page 122: ......
Page 127: ...1 GLOSSARY GLOSSARY ...
Page 128: ......
Page 135: ...1 INDEX INDEX ...
Page 136: ......