Crown ce 4000, Service Manual

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CE 4000 Service Manual
Theory of Operation 3-2
130485-1 Rev. B
©2002 Crown Audio, Inc.
pulses exiting the comparators long enough to keep
the current at an acceptable level.
If there is no current-limiting action, the balanced
output of U101 forms the positive portion of the
output waveform (Vp). The output of U103 is also
balanced and forms the negative portion of the
output waveform (Vn). These two balanced signal
lines are routed to the output stage drivers, U119 and
U123. If an audio signal is present at the inputs of the
modulators, the triangle wave will be compared to
a varying signal at the comparators and the outputs
of the NAND gates will be a 250 kHz pulse train in
which the widths of the pulses vary with the audio
amplitude.
This operation is described as Pulse Width Modulation
(PWM), as used in the BCA amplifi er.
3.1.4 Triangle Generator
The 250 kHz triangle wave has its origins from the
4MHz generator (clock generation is described in
the power supply section). After U224-A divides
the 500kHz square wave down to 250 kHz, U105
converts the signal from a 0V-5V square wave
to a –5V to +5V triangle wave that is extremely
accurate. R171, C159, C153, C154, R168, and R169
provide the feedback loop to the linear IC U105. The
potentiometer R170 allows the triangle wave to be
DC offset in order to change the overlap/underlap
characteristics of the output stage. Overlap/underlap
is analogous to the bias adjustment made in linear
output stages but it does not require a temperature
sense to prevent thermal runaway. The output of
U105 is routed to the non-inverting inputs of the
modulators.
A note on the triangle generator for channel two:
Before the frequency is divided down by two, the
500 kHz clock is inverted by U106-B. This effectively
shifts the channel two triangle wave 90 degrees from
that of channel one.
3.1.5 Output
The PWM modulated 250 kHz signals exit the modula-
tors and enter the output stage via optocouplers
U119 (Vp) and U123 (Vn). These optocouplers give
electrical isolation from the low voltage circuitry
to the high voltage output circuitry. The output of
U119 and U123 are then sent to the output MOSFET
drivers.
U120 and U121 are dual inverting high-speed
drivers designed to interface low current digital
circuitry (U119 and U123) with power MOSFETs (also
abbreviated FETs). U120 and U121 are used to drive
the gates of the output FETs (Q106-Q113).
In order to produce gate drive power to the drivers,
a fl oating supply is generated for the Vp side. This
supply uses U124-A and U124-B to divide the 500kHz
clock down to 125 kHz. The half-bridge driver U22
uses this 125 kHz clock to control the high-side and
low-side FETs in the dual FET IC U23 so that the
output of U23 is alternately connected to +15VPS
and ground . The rate of current rise is kept in control
by the inductance of transformer T101. The end result
is that the output of U23 is a square wave of 15V
amplitude and approximately 50% duty cycle that is
used as the primary excitation for the transformers.
The transformer provides the required isolation and
the secondary AC is converted back to DC by diodes
D131 and D132 and fi lter capacitors C316-C319. The
Vn side receives gate driver power from the fl yback
PWA (see below) and this power is referenced to
the –Vcc rail.
We pause now for a qualitative description of output
stage operation (refer to Figure 4.1). All parts to the
left of “Iout” are positive or “p” side parts and all
parts to the right of “Iout” are negative or “n” side
parts. The switches Swp and Swn are analogous to
the FETs. Quiescent operation will be considered
fi rst. At the start of a switching cycle Swp and Swn
are both turned on. Current fl ows from +Vcc, through
Swp, through Lp, through Ln, through Swn, and down
to –Vcc. The current rises at a controlled rate in the
Lp and Ln inductors (see the current diagram to the
right in Figure 4.1). Halfway through the cycle, the
switches turn off but the inductors have reached
a certain current fl ow (the peaks on the diagram)
and now must continue pushing current in the same
direction. The current continues to fl ow in the same
direction through the inductors but comes through the
diodes because the switches are open. Specifi cally,
current flows from –Vcc through D1, through Lp,
through Ln, through D2, and to +Vcc while ramping
down. At quiescent, the Lp and Ln currents cancel
so the net voltage developed at Iout across the
capacitor is zero. For positive voltage output, Swp
is left on longer than Swn and for a negative output
voltage, the opposite occurs. Note that for any output
voltage, the “on” time of both switches will overlap,
even if one is on longer than the other.