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Page 1: ...AY 1 COMPUTER SYSTEMS HARDWARE REFERENCE MANUAL HR 0004 Copyright 1976 1977 1978 1979 1980 1982 by CRAY RESEARCH INC This manual or parts thereof may not be reproduced in any form without permission o...

Page 2: ...Minnesota 55120 Revision Description January 1976 Original printing A r 1ay 1976 Repri nt wi th revi sion A 01 September 1976 Corrections to pages 3 20 3 27 4 9 4 10 4 28 4 36 4 43 4 55 and 4 57 B Oc...

Page 3: ...ave been reHritten Revision E obsoletes versions C and D of this publication E Ol May 1980 This change packet documents changes to the multiply functional unit that supports symmetrical multiply docum...

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Page 5: ...CONTROL UNIT FRONT END COMPUTER EXTERNAL INTERFACE MASS STORAGE SUBSYSTEM 3 COMPUTATION SECTION INTRODUCTION REGISTER CONVENTIONS OPERATING REGISTERS V regi sters V register reservations Vector contr...

Page 6: ...t Vector logical unit Vector population count unit Floating point functional units Floating point add unit Floating point multiply unit Reciprocal approximation unit 3 17 3 17 3 18 3 18 3 18 3 19 ARIT...

Page 7: ...g set Initiated by program exit Exchange sequence issue conditions Exchange package management MEMORY FIELD PROTECTION BA regi ster LA regi ster DEAD START SEQUENCE 4 INSTRUCTIONS INSTRUCTION FORMAT A...

Page 8: ...ump to ijkm set Boo to P Branch to ijkm if Ao 0 Branch to ijkm if Ao to Branch to ijkm if Ao positive Branch to ijkm if Ao negative Branch to ijkm if So 0 Branch to ijkm if So t 0 Branch to ijkm if So...

Page 9: ...from right 4 34 Form jk bits of one s mask in Si from left 4 34 Logical product of Sj to Sk to Si 4 35 Logical product of Sj and complement of Sk to Si 4 35 Logical difference of Sj and Sk to Si 4 35...

Page 10: ...lements 4 51 Logical sums of Sj and Vk elements to Vi elements 4 51 Logical sums of Vj elements and Vk elements to Vi elements 4 51 Logical differences of Sj and Vk elements to Vi elements 4 51 Logica...

Page 11: ...lements 4 63 Reciprocal iterations 2 Sj Vk elements to Vi el ements 4 63 Reciprocal iterations 2 Vj elements Vk elements to Vi elements 4 63 Floating sums of Sj and Vk elements to Vi elements 4 66 Flo...

Page 12: ...annels Input channels Output channels 16 bit high speed asynchronous channels Input channels Output channels 16 bit synchronous channels Input channels Output channels PROGRAMMED MASTER CLEAR TO XTERN...

Page 13: ...ter Interrupt countdown counter Clear programmable clock interrupt request APPENDIXES A SUMMARY OF TIMING INFORMATION B MODULE TYPES C SOFTWARE CONSIDERATIONS o INSTRUCTION SUMMARY 2240004 xi 6 23 6 2...

Page 14: ...nship of instruction buffers and registers Instruction buffers Exchange package General format for instructions Format for arithmetic and logical instructions Format for shift and mask instructions 1...

Page 15: ...word assembly disassembly 16 bit asynchronous input channel signa1 exchange 16 bit asynchronous output channel signa1 exchange 16 bit high speed asynchronous input channel signal exchange 16 bit high...

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Page 17: ...SECTION 1 INTRODUCTION...

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Page 19: ...and 12 output channels in the input output section connect to a maintenance control unit MCU a mass storage subsystem and a variety of front end systems or peripheral equipment The MCU provides for sy...

Page 20: ...ON 0 25 Mor 0 5 Mor 1 M 64 bit bi polar words I O SECTION 12 input channels 12 output channels I I I I 1 1 f i I I Ir CPU I ______ J I I I I I I I I 1 I I I I I I i I I I I I I I I I I L I J I I MASS...

Page 21: ...1 048 576 words of bi polar memory 64 data bits and eight error correction bits Eight or sixteen banks Four clock period bank cycle time One word per clock period transfer rate to B T and V registers...

Page 22: ...and subtractions produce either 24 bit or 64 bit results No integer divide instruction is provided and the operation is accomplished through a software algorithm using floating point hardware The inst...

Page 23: ...plications while its low cycle time is well suited to random access applications The phased memory banks allow high communication rates through the I O section and provide low read store times for vec...

Page 24: ...on in the same clock period This mechanism allows for chaining two or more vector operations together Chain operation allows the CRAY 1 to produce more than one result per clock period Chain operation...

Page 25: ...element segments and a possible remainder of less than 64 elements Generally it is convenient to compute the remainder and process this short segment before processing the remaining number of 64 eleme...

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Page 27: ...SECTION 2 PHYSICAL ORGANIZATION...

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Page 29: ...igh and extending outward about 2 1 2 ft are cabinets for power supplies and cooling distribution systems Viewing the cabinet from the top the chassis of the upper circle are labeled A through L proce...

Page 30: ...les 16 banks approx 115 standard module types Each module contains up to 288 IC packages per module Power consumption approximately 118 kw input for maximum memory size Refrigerant 22 cooled with refr...

Page 31: ...FTS LOGIC ADDR ADDERS I VECTOR I SHIFT CO TROL SIP I STR CO TROL BUFFERS SECDED VECTOR ADD XP DATA H I I I RECIP APPROX SEeDED ADDRESS fULTIPLY S POP rr ECTOR LOGICAL CO TROL SECDED j TO ECTOR i VECTO...

Page 32: ...sipation depends on module density The average module dissipation by usage is approximately 50 watts Two supply voltages are used for each module 5 2 volts for IC power 2 0 volts for line termination...

Page 33: ...t have internal regulation but depend on the motor generator to isolate and regulate inco ing power The power supplies use a twelve phase transformer silicon diodes balancing coil and a filter choke t...

Page 34: ...trol signals for execution of the master clear operation I O master clear operation dead dump operation and sample parity error operation The maintenance control unit MCU includes 1 A Data General ECL...

Page 35: ...in separate publications EXTERNAL INTERFACE The CRAY may be interfaced to front end systems through special interface controllers that compensate for differences in channel widths machine word sizes...

Page 36: ...CRAY l If this additional connection is made the station and mainframe may share the controller operation Either but not both can have an operation in progress at one time software interlocks must be...

Page 37: ...SECTION 3 COMPUTATION SECTION...

Page 38: ......

Page 39: ...units Vector and scalar processing is performed on data as opposed to address processing which operates on internal control information such as addresses and indexes The flow of data in the computatio...

Page 40: ...r Pnn 7 Sh i ft S 4 1 1 l r r I no r l I 52 Sk Add TOO 5 i SO Ah jkm Scalar Ak Exchange Functional Control Uni ts XA 1 Vector B77 I 1 Address Registers Con rol V i A VECTOR 1 Ai AD r LENGTH f 7 A6 Ak...

Page 41: ...CRAY I They enhance the speed of the system by satisfying the heavy demands for data that are made by the functional units A single functional unit may require one to three operands per clock period a...

Page 42: ...f the vector length VL register Vectors having lengths exceeding 64 are handled under program control in groups of 64 and a remainder A result may be received by a V register and retransmitted as an o...

Page 43: ...ve only one vector operation as the source of one or both operands No reservation is placed on the VL register during vector processing If a vector instruction employs an S register no reservation is...

Page 44: ...ation will use the results of the first operation and the operands in the register unaltered by the first operation However when the instructions chain together the second instruction does not receive...

Page 45: ...register At most one S register can be entered with data during each clock period Issue of an instruction is delayed if it would cause data to arrive at the S registers at the same time as data alread...

Page 46: ...the jk designator as described in section 4 of this manual A REGISTERS The eight 24 bit A registers serve a variety of applications They are primarily used as address registers for memory references...

Page 47: ...made is the Ao register The use of this register is implied in the following instructions 010 through 013 034 through 037 176 and 177 Refer to section 4 for additional information concerning the use o...

Page 48: ...as the address of the next instruction parcel to be executed FUNCTIONAL UNITS Instructions other than simple transmits or control operations are performed by hardware organizations known as functiona...

Page 49: ...rm 24 bit integer arithmetic on operands obtained from A registers and deliver the results to an A register The arithmetic is two s complement Address add unit The address add unit performs 24 bit int...

Page 50: ...ment subtraction for the 061 instruction occurs as follows The one s complement of the Sk operand is added to the Sj operand Then a one is added in the low order bit position of the result No overflow...

Page 51: ...an A register When the Vector Population Instructions Option is installed this unit also recognizes an additional instruction the 026ij1 instruction which returns a one bit population count parity ev...

Page 52: ...e for another operation Recursive characteristic of vector functional units In a vector operation the result register designated by i in the instruction is not normally the same V register as the sour...

Page 53: ...ts based on the results delivered to the second group of f u 2 elements and so on until the final group of f u 2 elements is generated as determined by the vector length As an example consider the sum...

Page 54: ...I9 Vl S9 V260 V2 S2 V1 60 V2 oo Vl o4 Vl I2 V1 2o V160 V261 V2 S3 V1 6I V2 oo Vl os VlI3 V1 21 V16I V262 V2 S4 V162 V2 00 V1os Vl14 V1 22 V162 V263 V2ss V1 63 V2 00 VI07 VIIS V1 23 V163 Note that if...

Page 55: ...e addition a one is added into the low order bit position of the result No overflow is detected by the unit The functional unit time for the vector add unit is three clock periods Vector shift unit Th...

Page 56: ...cuting a scalar instruction operands are obtained from S registers and the result is delivered to an S register When executing most vector instructions operands are obtained from pairs of V registers...

Page 57: ...Out of range exponents are detected as described under Floating Point Arithmetic However if both operands have zero exponents the result is considered as an integer product and is not normalized Funct...

Page 58: ...o 23 I I I SIGN 2 1 s COMPLEMENT INTEGER 24 BITS o 63 I I I SIGN 2 1 COMPLEMENT INTEGER 64 BITS Figure 3 2 Integer data formats I Multiplication of two integer operands may be accomplished using the f...

Page 59: ...63 I The exponent portion of the floating point format is represented as a biased integer in bits 1 through 15 The bias that is added to the exponents is 400008 The positive range of exponents is 4000...

Page 60: ...perand to zero Since So provides a 64 bit zero when used in the Sj field of an instruction a normalize of an operand in Sk can be performed using the following instruction 062iOk Si cont ins the norma...

Page 61: ...nderflow condition is detected when the sum of the exponents is less than or equal to 177778 and causes an all zero exponent and coefficient to be returned to the result register However if the sum of...

Page 62: ...l does not provide special hardware for performing double or multiple precision operations Double precision computations with 95 bit accuracy are available through software routines provided by Cray R...

Page 63: ...ed above the truncation The value determined by summing all carries produced by all possible com binations that could be truncated and dividing the sum by the number of possible combinations This aver...

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Page 65: ...times B equals B times A In a full precision rounded multiply 2 round bits are entered into the d t bOt to 2 50 d 2 51 d 11 d t t th pyraml a 1 POSl lon an an a owe 0 propaga e up e pyramid For a half...

Page 66: ...ion at step 1 is correct to 30 bits The additional Newton iteration at step 2 increases this accuracy to 47 bits This iteration is applied as a correction factor with a full precision multiply operati...

Page 67: ...cal products differences sums and merges A logical product is the AND function A A operand one operand two result logical difference operand one operand two result logical sum is operand one operand t...

Page 68: ...ction buffers and registers The P register is a 22 bit register which indicates the next parcel of program code to enter the next instruction parcel NIP register in a linear program sequence The upper...

Page 69: ...LIP holds the lower half Once an instruction enters the CIP register it must issue Issue may be delayed until previous operations have been completed but then the current instruction waiting for issue...

Page 70: ...INSTRUCTION BUFFERS There are four instruction buffers in the CRAY 1 each of which holds 64 consecutive 16 bit instruction parcels figure 3 7 Instruction parcels are held in the buffers prior to bein...

Page 71: ...condition if the instruction is in a different buffer than the previous instruction a change of buffers occurs necessitating a two clock period delay of issue An out of buffer condition exists when th...

Page 72: ...in instruction buffers prior to issue no attempt should be made to dynamically modify instruction sequences As long as the unmodified instruction is in an instruction buffer the modified instruction...

Page 73: ...bit limit requires that the absolute address be in the lower 4096 words of memory When an execution interval terminates the exchange sequence exchanges the contents of the registers with the contents...

Page 74: ...36 Interrupt on correctable memory error n 2 37 Interrupt on floating point error n 2 38 Interrupt on uncorrectable memory error n 2 39 Monitor mode Jl L ___Err r typ l tt __il _ _ _ f__ l 10 Uncorrec...

Page 75: ...red during the execution interval for a program through use of the 0021 and 0022 instructions respectively Bits 38 and 39 of n 2 are not altered during the execution interval for the exchange package...

Page 76: ...emory error flag is the only one of the nine F register flags that can be set The memory error flag can be set while in monitor mode 1 if either of the two memory parity error mode bits Bits 36 and 38...

Page 77: ...ence The B register T register and V register contents are not swapped in the exchange sequence The data in these registers must be stored and replaced as required by specific coding in the monitor pr...

Page 78: ...e address Active exchange package An active exchange package is an exchange package which is currently residing in the computer operating registers The interval of time in which the exchange package i...

Page 79: ...package at address zero is then moved into the operating registers and a program is initiated using these parameters The exchange package stored at address zero is largely noise as a result of the dea...

Page 80: ...read from memory for evaluation of the cause of program termination The monitor program selects an inactive exchange package for activation by setting the address of the inactive exchange package into...

Page 81: ...oper exchange package Consider the case v here exch nge packages exist for programs A 8 and C Program A is the monitor program program B is a user program and program C is an interrupt processing prog...

Page 82: ...d field of memory holding instructions and data The field limits are specified by the monitor program when the object program is loaded and initiated The field may begin at any word address that is a...

Page 83: ...execution interval for each exchange package The contents of LA are interpreted as the upper 18 bits of a 22 bit memory address The lower four bits of the address are assumed zero The LA register alw...

Page 84: ...nnected to the MCU and activates the input channel conected to the MCU subsystem All other input channels remain inactive The maintenance control unit then loads an initial exchange package and monito...

Page 85: ...SECTION 4 INSTRUCTIONS...

Page 86: ......

Page 87: ...aries is required Instructions have the following general form g h i j k m First parcel Second parcel Figure 4 1 General format for instructions Five variants of this general format use the fields in...

Page 88: ...mbined jk field specifies a shift or mask count This format is illustrated in figure 4 3 OPERATION CODE OPERAND AND RESULT REG j k 6 SHIFT MASK COUNT 16 81TS SHIFT MASK Figure 4 3 Format for shift and...

Page 89: ...R FORMAT Instructions that transfer data between the A or S registers and memory require a 32 bit format For these instructions a 4 bit operation code g is followed by two 3 bit fields and a 22 bit fi...

Page 90: ...formed by combining i j k and m The 25 bit field contains a parcel address and allows branching to a quarter word boundary The 3 bit i field is unused A program range error occurs if either of the two...

Page 91: ...perand value Ao o 1 So o 263 o Instructions are read a parcel at a time from the instruction buffers and delivered to the NIP register The instruction issues and is passed to the CIP register when the...

Page 92: ...ction consists of two parcels An x in the format signifies that the field containing the x is ignored during instruction execution Following the header information is a more detailed description of th...

Page 93: ...ccurs to the exchange package designated by the contents of the XA register The program address stored in the exchange package on the terminating exchange sequence is advanced by one count from the ad...

Page 94: ...er the real time clock register with Sj When the i designator is 0 1 or 2 the instruction controls the operation of the I O channels Each channel has two registers that direct the channel activity The...

Page 95: ...010 0011 0012 0013 and 0014 Aj or Sj or Ak Reserved Execution time Instruction issue 1 CP Special cases If the program is not in monitor mode instruction becomes a no op although all hold issue condit...

Page 96: ...truction loads the contents of the Sj register into the real time clock RTC register When the j designator is 0 the real time clock register is cleared When the k designator is 4 this instruction load...

Page 97: ...Exchange in process For 0014 Aj or Sj or Ak reserved Execution time Instruction issue 1 CP Special case For 0014jk If the program is not in monitor mode instruction becomes a no op but all hold issue...

Page 98: ...ontents of VL and then adding one to the low order six bits of the result For example if VL 100s then 100 1 77 and 77 1 100 However if VL 0 then 0 1 177 and 77 1 100 Thus the number of vector operatio...

Page 99: ...flag in the Mregister They do not check the previous state of the flag there is no way of testing the flag When set the floating point mode flag enables interrupts on floating point overflow errors a...

Page 100: ...tructions 146 and 147 in which an operation is performed depending on the contents of VM Hold issue conditions 034 037 in process Exchange in process Sj reserved 003 in process unit busy 3 CPs 14x in...

Page 101: ...f previously issued instructions an exchange sequence occurs to the exchange package designated by the contents of the XA reqister The program address stored in the exchange package is advanced one co...

Page 102: ...ime Instruction issue Both parcels of branch in a buffer and branch address in a buffer 7 CFS Both parcels of branch in a buffer and branch address not ina buffer 16 CPS Second parcel of branch not in...

Page 103: ...Both parcels of branch in the same buffer and branch address in a buffer 5 CPs Both parcels of branch in the same buffer and branch address not in a buffer 14 CPs Both parcels of branch in different b...

Page 104: ...n fo 11 ov ng the c2 11 by executin9 a branch to the contents of a B register Ho1d issue condi ti 9 034 037 n process Exchange in process Execution time Instruction issue Both parcels of branch in the...

Page 105: ...cess Ao busy in last 2 CPs Execution time Instructibn issue Both parcels of branch in the same buffer and branch address in a buffer 5 CPs Both parcels of branch in the same buffer and branch address...

Page 106: ...process So busy in last 2 CPs Execution time Instruction issue Both parcels of branch in the same buffer and branch address in a buffer 5 CPs Both parcels of branch in the same buffer and branch addr...

Page 107: ...formed by changing all one bits to zero and all zero bits to one Thus for the 021 instruction the upper two bits of Ai are set to one and the instruction provides a means of entering a negative value...

Page 108: ...ction enters the 6 bit quantity from the jk field into the low order 6 bits of Ai The upper 18 bits of Ai are zeroed No sign extension occurs Hold isssue conditions 034 037 in process Exchange in proc...

Page 109: ...J This instruction enters the low order 24 bits of Sj into Ai The high order bits of Sj are ignored Hold issue conditions 034 037 in process Exchange in process A register access conflict ft i reserve...

Page 110: ...contents of Bjk into Ai The 025 instruction enters the contents of Ai into Bjk Hold issue conditions 034 037 in process Exchange in process A register access conflict 024 only Ai reserved Execution t...

Page 111: ...n Sj Then the least significant bit which shows the odd even state of the I result is transferred to the least significa lt bit position of the Ai register The actual population count is not transferr...

Page 112: ...rs the result into the low order seven bits of Ai The upper 17 bits of Ai are zeroed The instruction is executed in the population leading zero count unit Hold issue conditions 034 037 in process Exch...

Page 113: ...is detected The 031 instruction forms the integer difference of Aj and Ak and enters the result into Ai No overflow is detected Hold issue conditions 034 037 in process Exchange in process A register...

Page 114: ...enters the low order 24 bits of the result into Ai No overflow is detected This instruction is executed in the address multiply unit Hold issue conditions 034 037 in process Exchange in process A regi...

Page 115: ...annel number when the j designator is nonzero The value of the current address CA register for the channel is entered into Ai when the k designator is an even number The error flag for the channel is...

Page 116: ...us ng nterrupt f L j 0 Ai current address of channel Aj if Aj 0 and k 0 2 4 6 Ai I O error flag of channel Aj if Aj 0 and k 1 3 5 7 Ai if Aj 1 2240004 2 CPs must elapse after an 0012xx instruction iss...

Page 117: ...See special cases for details The first register involved in the transfer is specified by jk Successive transfers involve successive B or T registers until B77 or T77 is reached Since processing of t...

Page 118: ...n out of range memory reference will cause an interrupt condition to occur For 034 036 the interrupt will occur in 2 CP 2 issues For 035 037 the interrupt will occur in 0 to 2 CP 2 issues 4 For 034 03...

Page 119: ...alue formed by the 22 bit jkm field and 42 upper bits of zero The complement is formed by changing all one bits to zero and all zero bits to one Thus for the 041 instruction the upper 42 bits of Si ar...

Page 120: ...one bits and if jk 77 8 Si contains zeros in all but the lowest order bit The 043 instruction generates a mask of jk ones from left to right in Si Thus for example if jk 0 Si contains all zeroed bits...

Page 121: ...1 0 1 0 Si 1 0 0 0 Sj is transmitted to Si if the j and k designators have the same non zero value Si is cleared if the j designator is zero The sign bit of Sj is extracted into Si if the j designato...

Page 122: ...j and Sk and enters the result into Si Bits of Si are set to one when the corresponding bits of Sj and Sk are the same as in the following example Sj 1 1 0 0 Sk 1 0 1 0 Si 100 1 Si is set to all ones...

Page 123: ...hen one of the corresponding bits of Sj and Sk is set as in the following example Sj 1 1 0 0 Sk 1 0 1 0 Si 1 1 1 0 Sj is transmitted to Si if the j and k designators have the same nonzero value Sk is...

Page 124: ...ifts Si 1eft j k places and enters the result into So The 053 instruction shifts Si right by 64 jk places and enters the result into So The 054 instruction shifts Si left jk places and enters the resu...

Page 125: ...ith Si initially the most significant bits of the double register The high order 64 bits of the result are transmitted to Si Si is cleared if the shift count exceeds 127 The 056 instruction produces t...

Page 126: ...uction forms the integer difference of Sj and Sk and enters the result into Si No overflow is detected Hold issue conditions 034 037 in process Exchange in process S register access conflict Si Sj or...

Page 127: ...Si The 063 instruction forms the difference of the floating point quantities in Sj and Sk and enters the normalized result into Si Hold issue conditions 034 037 in process Exchange in process Si regis...

Page 128: ...into Si The 065 instruction forms the half precision rounded product of the floating point quantities in Sj and Sk and enters the result into Si The low order 18 bits of the result are cleared The 06...

Page 129: ...ecution time Instruction issue 1 CP Si ready 7 CPs Special cases Sj 0 if j 0 Sk 26 3 if k 0 Arithmetic error allows 9 CP 2 parcels to issue before interrupt occurs if f p error flag is set 2240004 4 4...

Page 130: ...ximation instruction produces a result that is I accurate to 30 bits A second approximation ray be generated to extend the accuracy to 47 bits using the reciprocal iteration instruction Hold issue con...

Page 131: ...ransmit constant 2 0 to Si 071 i7k Transmit constant 4 0 to Si When the j designator is 0 the 24 bit value in Ak is transmitted to Si The value is treated as an unsigned integer The high order bits of...

Page 132: ...e conditions 034 037 in process Exchange in process Si register access conflict i reserved Ak reserved all instructions Execution time Si ready 2 CPs Instruction issue 1 CP S12ecial cases Ao 1 if k 0...

Page 133: ...monitor through use of the 0014 instruction The 073 instruction enters the 64 bit value of the vector mask VM register into Si The VM register is usually read after having been set by the 175 instruct...

Page 134: ...uction transmits the contents of register Sj to an element of register Vi The low order six bits of Ak determine the vector element for either instruction Hold issue conditions 034 037 in process Exch...

Page 135: ...h and I1h instructions transmit 24 bit quantities to or from A registers When transmitting data from memory to an ft register the upper 40 bits of the memory word are ignored On a store from Ai into m...

Page 136: ...ready for next scalar read or store 4 CPs Special cases Rank A conflict 3 CPs delay before Si ready Rank B conflict 2 CPs delay before Si ready Rank C conflict 1 CP delay before Si ready Hold storage...

Page 137: ...__________________________________________ _ These instructions are executed by the vector logical unit The number of operations performed is determined by the contents of the VL register All operatio...

Page 138: ...orresponding bit of Sj or Vj element are different from Vk element as in the following Sj or Vj element 1 1 0 0 Vk element 1 0 1 0 Vi element 0 lIe The 146 and 147 instructions transmit operands to Vi...

Page 139: ...1 Element 3 of V7 4 The remaining elements of V7 are unaltered 2 Suppose that a 147 instruction is to be executed and the following register conditions exist VL 4 VM 0 600000 0000 0000 0000 0000 Eleme...

Page 140: ...4 CPs 003 in process unit busy 3 CPs For 140 142 144 146 only Sj reserved For 141 143 145 147 only Vj reserved Execution time Instruction issue 1 CP Vi ready 9 CPs if VL 5 Vi ready VL 4 CPs if VL 5 Vj...

Page 141: ...d end with I elements specified by the contents of VL l All shifts are end off with zero fill The shift count is obtained from Ak and elements of Vi are cleared if the shift count exceeds 63 Hold issu...

Page 142: ...ister The 152 instruction performs left shifts In the general case element o of Vj is joined with element 1 and the 128 bit quantity is shifted left by the amount specified by Ak The 64 high order bit...

Page 143: ...ros Example Suppose that a 152 instruction is to be executed and the following register conditions exist VL 4 Al 3 El ement 0 of V4 a 00000 0000 0000 0000 0007 El ement 1 of V4 a 60000 0000 0000 0000...

Page 144: ...In the general case however instruction execution continues by joining element 0 with element 1 shifting the 128 bit quantity by the amount specified by Ak and transmitting the result to element 1 of...

Page 145: ...00 0000 0007 Instruction 153026 is executed and following execution register Vo contains the following values Element 0 of Vo a 00000 0000 0000 0000 0001 Element 1 of Vo 1 66000 0000 0000 0000 0000 El...

Page 146: ...Execution time continued Vj ready 5 CPs if VL 5 Vj ready VL CPs if VL 5 Unit ready VL 4 CPs Chain slot ready 6 CPs Special cases Ak 1 if k 0 2240004 4 60 E...

Page 147: ...formed is determined by the contents of the VL register All operations start with element zero of the V registers and increment the element number by one for each operation performed All results are d...

Page 148: ...Vi ready VL 5 CPs if VL 5 Vj or Vk ready 5 CPs if VL 2 5 Vj or Vk ready VL CPs if VL 5 Unit ready VL 4 CPs Chain slot ready 5 CPs Special cases For 154 if j 0 then Sj 0 and Vi element Vk element For...

Page 149: ...These instructions are executed in the floating point mUltiply unit The number of operations performed by an instruction is determined by the contents of the VL register All operations start with ele...

Page 150: ...ting point quantities in elements of Vj and Vk and enters the results into Vi The low order 18 bits of the result elements are zeroed The 164 instruction forms the rounded products cf the floating poi...

Page 151: ...xecution time Instruction issue 1 CP Vi ready 14 CPs if VL 5 Vi ready VL 9 CPs if VL 5 Vj or Vk ready 5 CPS if VL s 5 Vj or Vk ready VL CPs if VL 5 Unit ready VL 4 CPs Chain slot ready 9 CPs Special c...

Page 152: ...s determined by the contents of the VL register All operations start with element zero of the V registers and increment the element number by one for each operation performed All results are delivered...

Page 153: ...j and Vk rec dy 5 CPs if VL 5 Vj and Vk ready VL CPs if VL 5 Unit ready VL 4 CPs Chain slot ready 8 CPs Special cases Sj 0 if j 0 Arithmetic error allows a minimum of 13 CP 2 parcels and a maximum of...

Page 154: ...the divide sequence to compute the quotients of floating point quantities as described in Section 3 under Floating Point Arithmetic The reciprocal approximation instruction produces results that are...

Page 155: ...of 21 CP 2 parcels and a maximum of VL 20 CP 2 parcels to issue before interrupt occurs if f p error flag set If the Vector Population Instructions Option is installed the k field becomes relevant and...

Page 156: ...nstruction counts the number of bits set to one in each element of Vj The least significant bit of each element result shows whether the result is an odd or even number Only the least significant bit...

Page 157: ...ro when Vj element is nonzero If the k designator is 1 the VM bit is set to one when Vj element is nonzero and is set to zero when Vj element is zero If the k designator is 2 the VM bit is set to one...

Page 158: ...on time Instruction issue 1 CP Vj ready 5 CPs if VL 5 Vj ready VL CPs if VL 5 Unit ready except for 073 instruction VL 4 CPs Unit ready for 073 instruction VL 6 CPs SEecial cases k o or 4 V 1 bit xx 1...

Page 159: ...nted by one for each transfer Memory addresses begin with Ao and are incremented by the contents of Ak Ak contains a signed integer which is added to the address of the current word to obtain the addr...

Page 160: ...ccessive addresses are located in successive banks References to the samp bank can be made every 4 CPs or more Incrementing Ak by 16t places successive memory references in the same bank so a word is...

Page 161: ...SECTION 5 MEMORY SECTION...

Page 162: ......

Page 163: ...scheme used to address the independent banks it is possible to reference memory every clock period with a new request It is not possible however to reference anyone bank sooner than its 4 CP cycle ti...

Page 164: ...B and the third is rank C At each clock the contents of the registers are shifted down one rank until they are discarded unless a conflict arises in which case the conflicting address is held in rank...

Page 165: ...ating conditions on codes performing a mix of vector and scalar instructions the memory access will support four disk and three interface channels without degrading the CPU computation rate However a...

Page 166: ...e of the chips on the module Addressing a full million words with 8 bank phasing is possible In this case the right left bank select switch determines only whether the lower half of memory or the uppe...

Page 167: ...degradation for 8 banks as compared with 16 banks is not readily predictable since it largely results from an increase of memory conflicts for vector memory references For other differences refer to t...

Page 168: ...the horizontal row indicates that data bit contributes to the generation CPU of that check bit Thus check bit number 0 bit 264 is the bit making group parity even for the group of bits 21 23 25 27 29...

Page 169: ...X X X X x x x x x x x x X X X X X X X X X X X X X X X X x x x x x x x x X X X X X X X X X X X x x x x X X X X X X X X X X X X x x x x X X X X X X X X X X X X x x x x X X X X X X X X X X X X x x x x C...

Page 170: ...occurred within the data bits or check bits 4 If more than one syndrome bit is 1 and the parity of all syndrome bits is odd then a single and correctable error is assumed to have occurred The syndrome...

Page 171: ...SECTION 6 INPUT OUTPUT SECTION...

Page 172: ......

Page 173: ...eed asynchronous 3 16 bit synchronous disk channel Each type of channel has the same electrical interface to the I O cable but differs in timing protocol and data rates CHANNEL GROUPS Channels are div...

Page 174: ...signals are ready resume and disconnect These control signals coordinate the transfer of parcels over the channels The method of coordination varies among the types of channel the dif ferent methods...

Page 175: ...st continues until cleared by the monitor program at which time an interrupt from the next highest priority channel if present may be sensed INPUT CHANNEL PROGRAMMING To start an input operation the C...

Page 176: ...re the word count is exhausted The interrupt flag sets when a disconnect pulse is received or when an error condition is detected Setting the interrupt flag deactivates the input channel Input channel...

Page 177: ...odule channel The inter rupt is then generated and the channel is deactivated 2 Unexpected ready pulse DU Module DV DK asynchronous channel Data is held and the resume occurs when the channel is react...

Page 178: ...le the input channel is not active even if CA CL the ready is held until the channel goes active or until a Master Clear is received i e a Clear I O signal is generated by the MCU or a Programmed I O...

Page 179: ...on as the present word is transferred Then a disconnect pulse is sent to indicate the end of the transfer When the disconnect pulse is sent the channel is deactivated and an I O interrupt request is g...

Page 180: ...e as follows Parity Bit 0 Data Bits 20 23 Parity Bit 1 Parity Bit 2 Parity Bit 3 Data Bits 24 27 Data Bits 28 211 Data Bits 212 215 Parity bits are sent from the external device to the CRAY l at the s...

Page 181: ...1 2 3 4 5 6 7 8 9 10 11 12 13 Table 6 3 16 bit asynchronous output channel signal exchange DK module CRAY 1 Externa1 Activate channel set CL and CA Read word from memory and advance current address D...

Page 182: ...nnect is a signal sent from the CRAY l to the external device that means the transmission from the CRAY l is complete It is sent after the CRAY l has received the Resume from the last Ready The Discon...

Page 183: ...y bits are sent from the external device to the CRAY 1 at the same time as the data bits They are held stable in the same way as are the data bits Ready The Ready signal sent to the CRAY 1 indicates t...

Page 184: ...ulse 50 10 nanoseconds wide at the 50 voltage points Output channels Table 6 5 illustrates a general view of an output signal sequence Table 6 5 16 bit high speed asynchronous output channel signal ex...

Page 185: ...the leading edge of one Ready to the leading edge of the next Ready is 100 3 nanoseconds The leading edge of Ready may be used to time data sampling in the external device Resume Resume is sent from t...

Page 186: ...32 no Ready Resume Data 231 _216 no Ready Data 215 _2 no Ready Go to 8 Wait for Disconnect c If last word Disconnect Set interrupt and deactivate channel Parity Bits 0 through 3 Parity Bits 0 1 2 and...

Page 187: ...gid restrictions on its block lengths Input transmissions are limited to 1 or 4 or 512 64 bit words Cabling restrictions The synchronous channels use a fixed length cable providing constant propagatio...

Page 188: ...200 nsec pulse Ready Ready give the bit group odd parity Bit assignments are as follows Pari ty Bit 0 Data Bi ts 20 23 Parity Bit 1 Data Bits 24 27 Parity Bit 2 Data Bi ts 28 _ 211 Parity Bit 3 Data B...

Page 189: ...connected to this type of channel has rigid restrictions on its block lengths Output transmissions are limited to 1 or 512 64 bit words Cabling restrictions The synchronous channels use a fixed lengt...

Page 190: ...f the Master Clear signal Set the input channel limit This value may be the same value as used in steps 3 and 4 This turns off the Master Clear signal Device dependent this allows time for initializat...

Page 191: ...tus should be taken and discarded to remove any false status left by the Master Clear sequence Each of the four channel groups is assigned a time slot figure 6 2 which is scanned once every four clock...

Page 192: ...PUT READY CHANNEL CONTROL INPUT ADDRESS REG Ak tCH 2 6 ADV ADDR i I OUTPUT ADDRESS REG Ak CH 3 5 7 ADV ADDR i _ I O DATA FAN IN rio DATA FAN OUT I O ADDR FAN IN MEMORY DATA MERGE MEMORY DATA DISTR NO...

Page 193: ...uest every four clock periods To test for a memory bank conflict the lower four bitst of the memory address move through three l clock period registers The first register is rank A the second is rank...

Page 194: ...tting of the current and limit registers is limited to monitor mode REAL TIME CLOCK Programs can be timed precisely by using the clock period counter This counter is advanced one count each clock peri...

Page 195: ...al register II and the interrupt countdown counter ICD 0014j4 0014j5 0014j6 0014j7 Enter interrupt interval II register with Sj Clear the programmable clock interrupt request Enable the programmable c...

Page 196: ...st is set it remains set until a 0014j5 instruction clear programmable clock interrupt request is executed A programmable clock interrupt request can be set only after I the 0014j6 instruction has bee...

Page 197: ...APPENDIX SECTION...

Page 198: ......

Page 199: ...tructions reserve the floating point units Memory references may be delayed due to conflicts 2 The result register must be free 3 The operand register must be free 4 Issue is delayed 1 clock period if...

Page 200: ...emory may be considered a functional unit for timing considerations VECTOR INSTRUCTIONS Four conditions must be satisfied for issue of a vector instruction 1 The functional unit must be free Conflicts...

Page 201: ...is less than 5 The vector register used in a block store to memory 177 instruction is reserved for VL clock periods Scalar operand registers are not reserved Vector instructions produce one result pe...

Page 202: ...wo parcel instruction takes two clock periods to issue Instruction issue is delayed 2 clock periods when the next instruction parcel is in a different instruction parcel buffer Instruction issue is de...

Page 203: ...results if a 100 137 instruction is in the NIP register and a hold memory condition exists The delay will depend on the hold memory delay A delay of issue results if a 100 137 instruction is in the NI...

Page 204: ......

Page 205: ...data assembly 16 bit 12 I HS Instruction buffers 8 DM Output data disassembly 16 bit 12 HX Exchange sequence control 1 ON Input channel control tt J SERIES MODULES DO Output channel control tt JA CIP...

Page 206: ...FOnT A 2 VK Vector logical control 1 RI Form A12 VL Vector Pop Count Option It RJ FOnT A12 VR Vector registers 32 RK Form A Form A12 Z SERIES MODULES RL RM Form A2 10 ZB Storage w memory data buffers...

Page 207: ...but may also describe an operating system task that does not execute in monitor mode An object program may be a machine language program such as a FORTRAN compiler or it may be a program resulting fr...

Page 208: ...e floating point range error initiates an interrupt if the floating point mode flag is set in the mode register and monitor mode is not in effect The programmer has the capability via the 0022 instruc...

Page 209: ...y Vector Population Count Option only 2240004 0 1 DESCRIPTlON Error exit Error exit Set the channel Aj current address to Ak and begin the I O sequence Set the channel Aj limit address to Ak Clear cha...

Page 210: ...ords at B register jk to AO Store Ai words at B register jk to AO Read Ai words to T register jk from AO Read Ai words to T register jk from AO Store Ai words at T register jk to AO Store Ai words at...

Page 211: ...ry Memory Memory V Logical V Logical V Logical V Logical 0 3 DESCRIPTION Shift Sj and 5i right Ak places to Si Shift Sj and 5i right one place to Si Shift Si right Ak places to Si Integer sum of Sj an...

Page 212: ...4 DEseRI PTION Logical sums of Vj and Vk to Vi Logical differences of Sj and Vk to Vi Logical differences of Vj and Vk to Vi Clear Vi Transmi t Sj if VM bit 1 Vk if VM bit 0 to Vi Vector merge of Vk...

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