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Summary of Contents for BR3B8

Page 1: ...CONTROL DATA fi PUR A T ION CONTROL DATA 8RJ88 DISk STORAG UNIT J R F R NC MANUAL...

Page 2: ...CONTROL DATA j I 1 CONTROL DATA BR JB8 DISK STORAGE UNIT REfERENCE MANUALI...

Page 3: ...3 9 3 12 3 l3 3 16 3 18 thru 3 20 3 44 3 45 3 47 D Technical and editorial changes Changes affect pl l ges 3 78 3 79 3 80 7 25 75 Publication No 83301100 1973 1974 1975 by Control Data Corporation Pr...

Page 4: ...nt functions specifications and equipment number identification Section 2 Operation Describes and illustrates the location and use of all controls and indicators power on sequencing and disk pack inst...

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Page 6: ...1 1 3 1 3 1 4 1 4 1 4 1 4 Logic Functions 2 1 2 4 2 4 2 4 2 4 2 5 3 1 3 1 3 1 3 1 3 6 3 6 3 7 3 7 3 8 3 9 3 9 3 10 3 10 3 12 3 12 3 12 3 12 3 14 3 18 3 18 Basic Interface Description Unit Selection Se...

Page 7: ...ctor and Write Circuits 3 64 3 13 Velocity Detection 3 19 3 38 Write Data Serializer 3 66 3 14 Blower System 3 20 3 39 Write Serializer Timing 3 67 3 15 Logic Block Diagram 3 21 3 40 Write Irregularit...

Page 8: ...SECTION 1 GENERAL DESCRIPTION...

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Page 10: ...to 10 000 ft 3 05 km mean sea level 1000 ft to 35 000 ft 10 7 km POWER SPECIFICATIO S Typical Values Refer to Pub No 83301000 for additional power information Definitions Standby State dc power on spi...

Page 11: ...Cylinder Tracks lInch Track Spacing Rotational Speed Recommended Pack Access Mechanism 403 Tracks 1 Track Average Average Maximum Mode Bit Density Rate Quantity Read Write Width Quantity Maximum Lengt...

Page 12: ...LE ASSEMBLY BLOWER NOTE S DISK CLEANER ASSEMBLY USED IN OLDER UNITS TOP COVER ASSEMBLY The top cover assembly protects the drive assem blies during customer operations The pack cover is opened by mean...

Page 13: ...ment of the logic cards and dc power supply The chassis is hinge mounted for easy 1 4 access to the cards which plug in at the inner side of the chassis or to the backpanel terminals at the outer side...

Page 14: ...actory or by field personnel FCO changes 83301100 A are indicated by an entry on the FCO Log that accom panies each machine It is important that this log be kept current by the person installing each...

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Page 16: ...SECTION 2 OPERATION...

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Page 18: ...the panels and indicators on TAItT EEl EEl UNIT POWER OPERATOR CONTROL PANEL r T1I WIIIITI I 1I0UCT FAUI T a cabinet Table 2 1 describes the various panel controls and indicators LOGIC NUMBER LUG D TE...

Page 19: ...ontrol unit sequence power becomes available Switch causes a power off sequence when pressed while the indi cator is lighted The lens of this indicator is blank Indicator lights when read write heads...

Page 20: ...dc voltages in logic chassis can be GND test jacks measured do not use as a voltage source AC Power Supply Elapsed time meter Active when ac power is applied by UNIT POWER circuit breaker Records accu...

Page 21: ...imum disk pack life and reliability observe the following precautions 2 4 1 Store disk packs in a machine room atmosphere 600 F to gOOF 10 to 80 relative humidity 2 If a disk pack must be stored in a...

Page 22: ...83301100 A 4 Place the plastic canister over the mounted disk pack so that the post protruding from the center of the disk pack is recei ved into the canister handle 5 Twist the canister handle count...

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Page 24: ...SECTION 3 THEORY OF OPERAliON...

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Page 26: ...supply consisting of recti fiers and filters and the relays for power sequencing is mounted in the lower portion of the logic chassis Power supply cooling is accomplished by room air for the ac por I...

Page 27: ...Y CONVERSION CLEAR SIMPLIFIED SYMBOL D c OR E A D A A B A E OR Ie CLEAR PRnET I A JK f IIECI EARED rl f IIEsn o 0 I RECL AREO By I INYERTER i AND e DUAL AND lOR IA II IC OI E DUAL ANOIOR IUII IC O E W...

Page 28: ...ED FROM CONTROL INTERLOCKS SEE DRIVE MOTOR SEOU NCING I l fciRSEEK lNTERLOCK Xt lFR SEE AIT3 XMFR AIT2 XMFR 4tH HOY r Wdh p S 1 2 HYSTERFS S BRAKE KI COIL SENS NG SOARD SEE INTERLOCKS SEOUENCING DECK...

Page 29: ...DISTRIBUTION TO 20Y CONTROL INTERLOCK OK PACK ON NOT HEADS LOADED NOT AIR FLOW FAULT HEADS LOADED LOGIC a OR a K3 K3 GRD ENABLE FIRST SEEK INTERLOCK MOTOR START WINDING I I I I I L _____ J TO 24 VAC _...

Page 30: ...T TO DC PWR SUPPLIES I START D P KI CONTROL INT RLOCK SEE SEQUENCINGI UNLOADED L OA D E D_ c EN A II L E II ADS LOADED SW CRS lev HDS LOADED I LT VOLT FAULT DETECT OPEN ENABLE RETRACT SP DI K2 I O II...

Page 31: ...flow condition detected before heads are loaded will prevent energizing Motor Relay K3 Power On Sequence Power application to a unit is sequenced by logic and by relays in the power supply Refer to Fi...

Page 32: ...eads move into the pack the heads loaded switch closes This causes the following 83301100 C a Provides a control Signal to the logic for further loading unloading sequencing Figure 3 3 b Maintain a Mo...

Page 33: ...f Timing LOSS AND RECOVERY OF SPEED I I I L i T I I I I r II I I I I LOSS RECOVERY SHe All dc power supplies drop their outputs to zero and the logic is disabled Control Interlock Opening All relays o...

Page 34: ...ops Lou of DC Power If 20Y power is lost all relays open and the ac in put to the dc power supplies is opened The effect is the same as if all ac power were lost 8330ilOO c If 9 7v is insufficient the...

Page 35: ...ower is applied to the hysteresis brake 4 With K2 open a 20v removed from read write logic b Relay K5 opens The emergency re tract capacitor discharges through the voice coil to pull it back against i...

Page 36: ..._ I I L_ ________ _ flOCAi SPiNDLEI10T0RPOWEROFFl I I I I i I I I I I L __________ J Figure 3 6 Power Off Sequence BLOWER REMOVE I e POWER INPUT TO ALL DC POWER SUPPLl ES EX CEPT 20Y STAYS ON IF LOCAL...

Page 37: ...perature of the drive motor is monitored by an internal thermostat If the motor overheats the 3 12 thermostat opens This applies ac acroSS the DRIVE MOTOR circuit lJ aker coil to open the contacts The...

Page 38: ...TERLOCK ASSEMBLY rOISK PACK CANNISTER IJ 0 READ WRITE HEADS 19 TRACK SERVO H AD I SPINDLE SPINDLE DRIVE PULLEY PACK SENSOR ASSEMBLY SPEED SENSOR GROU NG DRIVE MOTOR PULLEY DISK CLEANER ASSEMBLY USED I...

Page 39: ...otor power to an improperly con figured unit Actuator The actuator consists of the carriage actuator hous ing and magnet assembly The actuator Figure 3 9 is the device that supports and moves the read...

Page 40: ...magnet assembly and the lone track servo head installed on the head arm re ceiver The transducer is a two piece device one piece stationary and the other movable Refer to the Transducers paragraph for...

Page 41: ...ates disk pack rotation and a First seekl Interlock cycle in older units a disk clean ing cycle In units having a disk cleaning cycle actual cleaning time is approximately five seconds total cycle tim...

Page 42: ...the logic This causes the voice coil to drive the carriage in reverse from its current location toward the re tracted stop Either normal or emergency methods can be used Refer to Power Off Sequence p...

Page 43: ...sducer The logic then shapes this signal into a 55 microsecond pulse As long as the speed ex ceeds 3000 rpm one of these pulses will be sensed at least once each 20 ms A sensing circuit within the mon...

Page 44: ...tor is energized during the Power On sequence and starts a 15 second approximate cycle The cam is designed so that the brushes swing in and out of the disk area during the first five secoi1ds of the c...

Page 45: ...sical damage and greatly reduces the possibility of contamination of the disk pack record ing surfaces LOGIC FUNCTIONS The logic functions perform ed by the drive are sub divided as follows 3 20 Basic...

Page 46: ...2 N T L DATA STROBE I R I 0 L L E R DEVICE CLOCK I SECTOR MARKS I STATUS REQUEST ADDRESS STATUS 9 A definition of the I O lines is provided in Table 3 1 Table 3 2 defines the functi on control codes...

Page 47: ...d valid This line signals the controller that the drive has recognized its address on the Device ID lines and that it has decoded the command on the Function Control lines and is executing that comman...

Page 48: ...l Strobe which in the Select and Reserve command remains high the follow ing information is present on the Address Status lines Bit 0 Reserved Indicates that the drive is reserved by the requesting ch...

Page 49: ...aces the contents of the Fault register on the Address status lines Fault register is cleared by the trailing edge of the Read Fault Function Control Strobe Clear or Device Reset Following is the defi...

Page 50: ...ed If the parity error occurred on the reserved channel the Not Operational bit is set If the parity error occurred on the non reserved channel the Not Operational bit will be sent to that channel onl...

Page 51: ...en on the disk with the head selected by the Head register This command is used to terminate a Read or Write operation This command causes the positioner to move toward the spindle the number of track...

Page 52: ...SU has strobed the ADDSTAT lines The controller may drop FCS any time after senSing CSA CSA will drop 250 J lsec maximum after the fall of FCS DEVICE ID FCN ADDSTAT FCS Operational Status Byte The Ope...

Page 53: ...N for definition of faults 2 The first seek is not completed 3 A parity error on the Device ID lines sets Not Operational to the channel sending the Status Request High as long as the Operators panel...

Page 54: ...e daisy chain but only the drive with the Logical Address Plug LAP that matches the ID code will decode the command In order for a drive to communicate with the controller it must recognize its ID cod...

Page 55: ...on Error during the last 32 tracks except last track of all Seek operations Provides coarSe Position Error signal the amplitude of which is proportional to the number of tracks to go Amplitude is clam...

Page 56: ...ity between each of the last 32 track pulses of a seck Integrator is clamped off to gain of zero at all other times Integrator output is a sawtooth waveform applied to input of desired velocity functi...

Page 57: ...se to velocity signal The combination of the position error and velocity signals controls voice coil current to bring positioner into On Cylinder position Monitors fine position signal when T 1 When s...

Page 58: ...NAL AMOUNT OF OFFSET COMMANOEO D THESE SIGHALS ARE ApPLIED TO MONHOI AND MVLTIPLU LOGIC FOR OIAGNOSTICS en T Z INrEGJl ATOF PUU OR CLAMP FINE e en 81T 0 UART SEEK P Vvo u D 31 i IPS 1 1 c e iff lIPS 1...

Page 59: ...3 34 Accelerate Phase This phase is controlled largely by the position error signal The controller loads the difference counter with the complement of the seek length For exam ple if the heads are pr...

Page 60: ...CHANGE CAUSED BY ADOITION OF INTEGRATED VELOCITY SIGNAL TO POSITION CONVERTER SIGNAL OUTPUT DECRE SES WITH EAC eYLIN DER PU L SE INE L TCH SETS WHEN T I AND INTEGRATED V LOCITY 1 28V DESIREO VElOCITY...

Page 61: ...ing Stop Phase Stop Phase begins when the difference counter indi cates that there is one track to go When T l the velocity integrator signal is pulled back to zero by the cylinder pulse Its output in...

Page 62: ...nd direction determined by the Set Differ ence command and the Offset Byte on the ADDSTAT lines Heads must be On Cylinder and a Diagnostic command along with the Diagnostic Mode byte on 83301100 A the...

Page 63: ...his circuit is derived from the track servo head Figure 3 20 This head is physically similar to the read write heads except that it does not write The head reads information from the servo track surfa...

Page 64: ...m followed immediately by a positive going waveform 83301100 A The dibits are analyzed by the positive and negative gates Each output switches to the low state when it senses its respective dibit The...

Page 65: ...EG4TIV EY N tHelTS TtHO TO DRIV Tf AC S RIJO SIGNAL POS1TIV TRA K SERVO SIGNAl IS lUI WHEN AMPLITUDES Of POSITIVE ANO NeGAlIvE 018115 ARE OUAL Sr 60LOG I q INHIBIT WHEN INPUT IS tOW r 5UMM tfG POINT O...

Page 66: ...TS EVEN 0181T5 TRACK SERVO EXAGGERA TEO I LEAVING 000 0161T TRACK I 0181T 0181T 1 251 5 u r ON CYLINDER j r APPROACHING EVEN 1 0181T TRACK r NOTE TIMING SIMPLIFIED FOR CLARITY SERVO HEAD CENTERED BETW...

Page 67: ...al to velocity the input to the integrator and time provided by the integrator capaci tor Thc output which is a positive going ramp during forward seeks represents distance travelled It is pulled back...

Page 68: ...e circuit causes both SERVO HEAD PATH ACROSS OIBIT BANDS POSITIVE OIBIT NEGATIVE OIBIT DISK MOTION t DATA 000 TRACK w m m r J r r L TRACK 0 EVEN H TRACK Ii DATA _ _ _ _ _ TRACK I RESULTANT OF POS AND...

Page 69: ...and 7 Initiation of the function occurs when the START switch is pressed Figures 3 24 and 3 25 Refer to the power supply discussion 3 44 in this section for additional sequencing information Busy sta...

Page 70: ...co w w o o o W I j CJ1 BRUSH CYCL E USED IN OLDER UNITS Figure 3 24 SHEET 2 SHEET 2 8H IO IA First Seek Flow Chart Sheet 1 of 2...

Page 71: ...LAT l H MEADS UNLOAD _ITIIG CLEAR SELECT LOCI GENERATE 011 CYLIIlDER CARRIAGE MOYES UIllDER CONTROL OF FINE SIGNAL IIAX I IENERATE UIIIT READY SET SEEI COIIPLETE EYEN DI 1 S DETECTED APPROACHING TRAC...

Page 72: ...Y IC5 PICKED WHEN KZ PICKS 100AD FF CAUSES LOAD GATE TO APPLY SEEIC FWD YOLTAIIIE 10 YOICE COIL SUMMING AMPL COAItSE AND FINE GATES INHIIITED CYLINDER REGISTER lET 10 ZlItO AND DIFFERENCE COUNTU lET T...

Page 73: ...linder Register command a Bits 1 and 3 on the ADDSTAT lines are raised transmitting a new cylin der address of 16010 b The new cylinder address is loaded into the Cylinder Address register 2 Controlle...

Page 74: ...NE FF NO INVERT TRACK SERVO 51 GNAL INPUT TO FINE POSITION AMPL E I SHEET 2J POSITION CON vERTER OUTPUT CLAMPED AT MAXIMUM OUTPUT CONTROLLER SENDS SEEK FORWARD COMMAND Q DIFFERENCE IS DECIMAL 150 TRAC...

Page 75: ...BY I HEAD MOTION OATA TRACKS SERVO DI BITS TRACK SERVO FINE SERVO VELOCITY XDCR OIFF CNTR 160 16 1 157 IrS 19 I I IEVENI IODD IEVEN I 000 I I A t I I I THESE SIGNALS l SUMMED TO TION r CONTROL MO 7 o...

Page 76: ...Commal oa l j at sample time Difference Counter is loaded with of seel length increments with each gaterl cylin __ _ Complement of 15010 is 36110 Counter Positioner acc Clerates to a iw1 l 6 j i r xim...

Page 77: ...e to the summing amplifier Since the carriage is stationary no velOcity signal exists to balance the position error and forward motion of the positioner begins With the position error signal clamped a...

Page 78: ...le fine servo position error signal If the seek had been to an odd cylin der Odd would have been set and the track servo signal would not have been inverted As the posi tioner approaches track 160 the...

Page 79: ...C J I Ul 00 V V o o o 0 8HI4 Figure 3 28 RTZS Flow Chart...

Page 80: ...condition if dibits are lost for more than 200 ms The Fault FF is set to prevent another irst Seek until the Fault indicator has been cleared 83301100 A MACHINE CLOCK CIRCUIT The machine clock circuit...

Page 81: ...a dub in pulse the circuit may not be in synchronization with real data when it is received It would then take some time before synchronization could be attained The 5 ms dub in inhibit pulse fires t...

Page 82: ...ero with each clock pulse I 1 600 NS 1 INDEX PATTERN j 1 ODD EVEN Dt alTS 80e KHZ CIJ CK CD EVEN DI BITS K2900 D1 BITS PRESENT K2901 COUNTER W 2900 I 0 j l 0 2 3 4 6 DECODE H2900 I S 4 INDEX sET 1 290...

Page 83: ...e 806 KHi FF INDEX SECTOR PULSE 806 KHi FF SECTOR PULSE Note that Index is inhibited while the heads are over either a forward or reverse EOT area Sectc rr Circuit The sector circuit Figure 3 31 permi...

Page 84: ...one eleventh of a disk rotation Since the Not Last Sector FF was set at Index to 3 32 for Sector Circuit the Sector Counter pulse then sets the Sector Pulse FF The Sector Pulse is returned to the Sect...

Page 85: ...the equivalent of a miniature bar magnet with a North 3 60 pole and a South pole The writing process orients the poles to permanently store the direction of the flux field as the oxide passes beneath...

Page 86: ...ATIVE HEAD TO SURFACE MOTION REPRODUCING READ OPERATION 7SIBA Figure 3 34 Reading Data 7S17A 000 the cylinder nearest the outside edge of the disk Data record format is a function of the operating to...

Page 87: ...riz ed as follows 1 There is a flux transition for each I bit at the time of the 1 2 There is a flux transition between each pair of 0 bits 3 There is no flux transition between the bits of a 10 or 01...

Page 88: ...ad address into the Head Address register Figure 3 37 For purposes of this discussion assume that head 02 is the head to be selected In order to select head 2 bit 7 of the ADDSTAT lines must be high W...

Page 89: ...REAO DATA I PREAMP EO I ENABLE I I PREAMP I EVEN iflf CURRENT SENst AC WRIT FAULT I I tr G R 0 U N D_ EN A 8 L E _ _4 _ _l1 0 I I VHJI VHt I I I U V READ WRITE I L ________ _ _______ 1 HEAD 01 SCE se...

Page 90: ...his discrete component circuit QEL restores symmetry to the data signals 83301100 A that may have been lost in the write chain Refer to the Cards manual see Preface for a detailed description of this...

Page 91: ...e 3 39 they are shown 90 degrees out of phase In order to strobe the data off the lines in the center of the pulse when the data is stable Data Strobe is locked to one cycle of the 1 2 Clock FF This i...

Page 92: ...condition exists because no electromechanical device can be perfect In an ideal world the flux reversal command by the write toggle would be instantaneous as shown in the 83301100 A Ideal Recording p...

Page 93: ...ltage But in the real world it takes time for the current to reverse the flux change is not instantaneouS Furthermore heads must fly a finite distance from the disk The greater the distanee between th...

Page 94: ...n the 01 and only 1 0 cell between the 11 As a re sult the squeezing of the cells causes the mathe matical average the actual readback voltage to shift the apparent peak to the left This is early peak...

Page 95: ...ed to the write toggle 2 If frequency is decreaSing the apparent readback peak Figure 3 41 would occur later than normal To compensate for this the data is written earlier than nominal Early Gate is e...

Page 96: ...ATE wRtTE DATA TO WRiTE TOGGLE l ISS NI I o o o o o o o o I I I I I IT 0 ITJ I I I I I 001 011 I I 10 I I o 0 N N T T I I M E I I I E I I l j I l 1 i hh I L JEl L _r lL ___ JrE iL ___iLL JL L o o o o...

Page 97: ...zero cross detector in the high reso lution channel and through the low pass filter to the 3 72 zero cross detector in the low resolution channel The filter lowers the resolution of the Read signal b...

Page 98: ...155 NS I 30 tlS 1 I i S ET J DELAY I ZERQ CROSSOVER A4500 J J i tI 45 NS PULSE GENERATOR X4500 2 I g gg I Io 150 NS RESET LATCH 14505 1 I It IOO NS A4501 40 NS j PULSE DATA FORHER PULUS ERO_CROSSOVER...

Page 99: ...ll not occur during PI or P2 time for example in a 10 pattern Y Enable acts as a fake data pulse to set the FF to maintain reasonable frequency control 3 74 The Comparator FF output is integrated and...

Page 100: ...EARLY DATA x DS Y DISABLE Y ENABU CO PARATOR FF e 2 Y ENABLE P4 2 DATA PATTERN r 14 1 HS t o Figure 3 45 Phase Lock Oscillator Circuit NOTES 2 K l f J FF TO _I C24 I DATA EPARATOft 12 DELAYS VARY TO...

Page 101: ...H 0 FROM LOGIC DIAGRAMS TO SIIoIPLIFY CIRCUIT FUNCTION ct G NOIoII AL TIMING SHOWN ARC DR RRC SHIFTS LEADING EDGE OF STROBE t8 NS AS SHOWN ADYAHCEll RETARD G I l DATA STROBE f 2 DATA WINDOW FF DATA SE...

Page 102: ...zer almost one cell time after it is detected 83301100 A Read Data Deserializer Circuit The Read Data Deserializer is used to convert the serial data read from the disk into the two bit parallel forma...

Page 103: ...G K3601 i READ GATE 5 r READ DATA L p G 5 K360 RESET R W HEADS LOADED J A I 5 SHIFT READ DATA REG B J J r G G K 602 K3605 L J t G 3604 I i READ L STROBE I J G L I G K3608 L L K3606 I D r D G L G K490...

Page 104: ..._ n n n n n n n __ DATA K4702 DATA aUFF K3600 SHIFT REG A K3601 SHIFT REG B K3602 READ STROBE K3606 READ DATA REG A K3605 READ DATA REG B K3604 READ DATA REG C K3608 K4900 K4901 READ DATA aO 14914 REA...

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Page 106: ...lPMfIIT NO AND DIIC I TIOIi 110 SEIIIES COOE From Equipment Nameplate FCO LOfI 1111 Fe o s INCORPORATED INTO EQUIPMENT This form is not int nd d to be u8 d as an order bJar k Your luati ln of th s man...

Page 107: ...E STAMP NECESSARY IF MAILED IN U S A POSTAGE WILL 8E PAID 8Y CONTROL DATA CORPORATION Technical Publications Department 7801 Computer Avenue Mituleapolis MN 55435 I FIRST CLASS I PERMIT NO 8241 MINNEA...

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