ComSync/PCI-104 Gen 3
Users Guide
www.connecttech.com
Document: CTIM-00122
Revision: 0.01
Page 11 of 11
Connect Tech Inc. 800-426-8979 | 519-836-1291
Date: 2017-01-26
ESCC DMA Data Transfers
The Zilog ESCC device has the ability to “signal” the need for data transfers to/from its internal data FIFO’s,
which operates independently from its interrupting mechanism. This ability has been exploited in this product
with the inclusion of an FPGA. Internal to the FPGA is 2 independent DMA controllers, each with dual
memory buffer access capability. Also with the FPGA is a total of 2048 bytes of FIFO (512 bytes per port /
direction).
Once initialized by software, the data transfers between the computer memory and the ESCC are completely
autonomous, with the DMA controllers generating interrupts when transfer buffers are completed, or errors
occur.
Detailed Technical Manual
A companion detailed technical manual for this product is available upon execution of an Non-Disclosure
Agreement (NDA). This manual contains technical details that software developers would need to incorporate
this product in their system.
