3.0 Electrical Interfaces
Fusion 878A
3.2 PCI Bus Interface
PCI Video Decoder
3-8
Conexant
100600B
3.2 PCI Bus Interface
The PCI local bus is an architectural, timing, electrical, and physical interface that
allows the Fusion 878A to interface to the local bus of a host CPU. The Fusion
878A is fully compliant with PCI Rev. 2.2 specifications.
The supported bus cycles for the PCI initiator and target are:
•
Memory read
•
Memory write
The supported bus cycles for the PCI target only are:
•
Configuration read
•
Configuration write
•
Memory read multiple
•
Memory read line
•
Memory write and invalidate
Memory write and invalidate is treated in the same manner as Memory write.
Memory read multiple and Memory read line are treated in the same manner as
Memory read.
The unsupported PCI bus features are:
•
64-bit bus extension
•
I/O transactions
•
Special, interrupt acknowledge, dual address cycles
•
Locked transactions
•
Caching protocol
•
Initiator fast back-to-back transactions to different targets
As a PCI master, the Fusion 878A supports agent parking, AD[31:0],
CBE[3:0], and PAR driven if GNT is asserted and follows an idle cycle
(regardless of the state of bus master).
All bus commands accepted by the Fusion 878A as a target require a
minimum of three clock cycles. This allows for a full internal clock cycle address
decode time (medium DEVSEL timing) and a registered state machine interface.
Write burst transactions can continue with zero wait state performance on the
fourth clock cycle and onward (unless writing to video decoder/scaler registers).
All read burst transactions contain one wait-state per data phase.
provides a block diagram of the PCI video interface.
provides a block
diagram of the PCI audio interface.
