Fusion 878A
2.0 Functional Description
PCI Video Decoder
2.18 Digital Audio Packetizer
100600B
Conexant
2-55
2.18.3 FIFO Interface
The audio FIFO de couples the high-speed PCI interface from the slow audio data
packetizer. The size chosen provides for efficient PCI bursts and effective PCI
bus latency tolerance:
FIFO_WR must not be active for two consecutive FWCLK cycles. Thus, each
word write must be followed by at least one dead cycle. FIFO_WR write data rate
must also be less than the FRCLK rate. Since FWCLK = FRCLK = PCI-CLK for
this instance, the write rate is not an issue.
The 6-bit DWORD counter indicates the number of DWORDs stored in the
FIFO. It is cleared when FIFO_ENABLE is reset to 0. Otherwise, FIFO_WR –>
cntr++, and FIFO_RD –> cntr--. This counter is part of the DAP block.
The 6-bit DWORD counter will be available for monitoring on GPIO[13:8]
during debug mode (similar to the video DWORD counter monitor on
GPIO[7:0]).
illustrates the FIFO interface.
FSIZE = 35
FFULL = 34
FAFULL = 32
Figure 2-24. FIFO Interface
6-Bit DWORD Counter
FIFO_RD
FO[35:0]
FIFO_ENABLE
FRCLK
FIFO_WR
FI[35:32]
FI[31:0]
FWCLK
FIFO
35 x 36
Status
Data
879A_028
