2.0 Functional Description
Fusion 878A
2.12 DMA Controller
PCI Video Decoder
2-38
Conexant
100600B
The software will set up a pixel data flow by creating a RISC instruction
sequence in the host memory for the odd and even fields. The DMA controller
normally branches through the RISC instruction sequence via JUMP instructions.
The RISC program sequence needs to be changed only when the parameters of
the video capture/preview mode change. Otherwise, the DMA controller
continuously cycles through the same program, which is set up once for control of
an entire frame.
2.12.3 RISC Instructions
There are five types of packed mode RISC instructions—WRITE, WRITEC,
SKIP, SYNC, and JUMP—that control the data stored in the FIFO. Three
additional planar mode instructions exist, which replace the simple packed mode
WRITE/SKIP instructions. Instruction details are listed in
controller switches from packed mode to planar mode or vice versa based on the
status codes flowing through the FIFOs along with the pixel data.
Table 2-10. RISC Instructions
(1 of 5)
Instruction
Opcode
DWORDs
Description
WRITE
0001
2
Write packed mode pixels to memory from the FIFO beginning at the specified
target address.
DWORD0:
[11:0]
Byte count + Byte offset
[15:12]
Byte enables
[23:16]
Reset/Set RISC_STATUS
[24]
IRQ
[25]
Reserved
[26]
EOL
[27]
SOL
[31:28]
Opcode
DWORD1:
(1)
[31:0]
32-bit target address
Byte address of first pixel byte.
NOTE(S):
(1)
[1:0] is the Byte offset.
