Fusion 878A
2.0 Functional Description
PCI Video Decoder
2.11 Video and Control Data FIFO
100600B
Conexant
2-33
2.11.2 FIFO Data Interface
Loading data into the FIFO can begin only when valid pixels are present during
the even or the odd field. The pixel DWORD Pixel Data (PD) [31:0] is stored in
FI[31:0], and the video control code STATUS[3:0] is stored in FI[35:32]. The
VBI data will be included in the captured sequence if VBI capture capability is
enabled.
Four bits of STATUS are used to encode information about the pixel data and
the state of video timing unit (see
). Video timing and control
information, along with the data stream, passes through the FIFO. The FIFO
buffer isolates the asynchronous video input and PCI output domains. Control of
the input stream can occur only from the video timing unit of the video decoder
and from the configured registers. The interaction and synchronization of the
DMA controller and the RISC instruction sequence relies solely on the output
side of the FIFO.
Capturing data to the FIFO always begins with a FIFO mode indicator code
followed by pixel data. The FIFO mode indicator is stored in the FIFOs at the
beginning of every capture-enabled field, when the data format is changed
mid-field such as transitioning from packed VBI data to planar mode, and when
video capture of a field is asynchronously enabled. The mode status codes are
always stored in planar format. FIFO1 receives two copies of the status code,
while FIFO2 and FIFO3 each receive one copy.
The SOL code is packed in the FIFO with the first valid pixel data byte, which
is the first pixel DWORD for the scan line. The EOL code is packed in the FIFO
with the last valid pixel data byte, which is the last DWORD location written to
the FIFO for the scan line. The EOL code indicates 1–4 valid bytes. The
VRE/VRO code is stored in the FIFO at the end of a capture-enabled field. The
DMA controller activates the appropriate PCI byte-enable by the time a given
DWORD arrives on the output side of the FIFO.
The DMA controller guarantees that the FIFO does not fill; therefore the
VDFC has no responsibility for FIFO overruns. The DMA Controller will be able
to resynchronize to data streams that are shorter or longer than expected.
Table 2-7. Status Bits
Status[3:0]
Code
Description
0110
FM1
FIFO Mode: packed data to follow
1110
FM3
FIFO Mode: planar data to follow
0010
SOL
First active pixel/data DWORD of scan line
0001
EOL
Last active pixel/data DWORD of scan line, 4 valid bytes
1101
EOL
Last active pixel/data DWORD of scan line, 3 valid bytes
1001
EOL
Last active pixel/data DWORD of scan line, 2 valid bytes
0101
EOL
Last active pixel/data DWORD of scan line, 1 valid byte
0100
VRE
VRESET following an even field–falling edge of FIELD
1100
VRO
VRESET following an odd field–rising edge of FIELD
0000
PXV
Valid pixel/data DWORD
