5.0 Control Register Definitions-Function 0
Fusion 878A
5.3 Local Registers (Memory Mapped)
PCI Video Decoder
5-8
Conexant
100600B
5.3 Local Registers (Memory Mapped)
Fusion 878A’s local registers reside in the 4 kB memory addressed space reserved for each function. All of the
registers correspond to DWORD or a subset thereof. Local registers may be written to or read through the PCI
bus at any time. Internal addressing of the Fusion 878A local registers occurs via AD[11:2] and the byte enable
bits of the PCI bus. The local memory-mapped register address locations are specified as 12-bit offsets to the
value loaded into the functions memory base address register. The 8-bit byte address for each of the following
register locations is {AD[11:2], 0x00}. Any register may be written or read by any combination of the byte
enables.
Data to and from the video decoder/scaler registers and VDFC comes from PCI byte lane 0 (AD[7:0]) only. If
the upper byte lanes are enabled for reading, the data returned is 0. Thus, each register is separated by a byte
address offset of four. All non-used addresses are reserved locations and return an undefined value.
The scaling function needs to be controlled on a field basis to allow for different size/scaled images for
preview and capture applications. All registers that affect scaling, translation, and capture on the input side of
the FIFO provide for even and odd field values that switch automatically on the internal FIELD signal.
The following types are used to specify how the Fusion 878A registers are implemented:
ROx
Read only with default value =
x
.
RW
Read/Write. All bits initialized to 0 at RST, unless otherwise stated.
RW*
Same as RW, but data read may not be same as data written.
RR
Same as RW, but writing a 1 resets corresponding bit location. Writing a 0 has no effect.
