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6–24

Privileged Architecture Library Code

Alpha 21264/EV67 Hardware Reference Manual

Performance Counter Support

6.10.3.4 Counter Modes for ProfileMe Mode

Table 6–14 shows the counter modes that are used with ProfileMe mode.

Table 6–14 ProfileMe Mode PCTR_CTL Input Select Fields

SL0[4]

SL1[3:2] PCTR0

PCTR1

1

00

Retired instructions

Cycle counting

1

01

Cycle counting

Inum retire delay

1

10

Retired instructions

Bcache miss or long latency probes

1

11

Cycle counting

Mbox replay traps

Summary of Contents for 21264

Page 1: ...l is directly derived from the internal 21264 EV67 Specifications Revi sion 1 4 You can access this hardware reference manual in PDF format from the following site ftp ftp compaq com pub products alphaCPUdocs Revision Update Information This is a revised document It supercedes the Alpha 21264A Microprocessor Hardware Reference Manual DS 0028A TE ...

Page 2: ...IES OF MERCHANTABILITY FITNESS FOR PARTICULAR PURPOSE GOOD TITLE AND AGAINST INFRINGEMENT This publication contains information protected by copyright No part of this publication may be photocopied or reproduced in any form without prior written consent from Compaq Computer Corporation Compaq Computer Corporation 2000 All rights reserved Printed in the U S A Alpha 21264 EV67 Hardware Reference Man...

Page 3: ...nteger Issue Queue 2 6 2 1 1 7 Floating Point Issue Queue 2 7 2 1 1 8 Exception and Interrupt Logic 2 8 2 1 1 9 Retire Logic 2 8 2 1 2 Integer Execution Unit 2 8 2 1 3 Floating Point Execution Unit 2 10 2 1 4 External Cache and System Interface Unit 2 11 2 1 4 1 Victim Address File and Victim Data File 2 11 2 1 4 2 I O Write Buffer 2 11 2 1 4 3 Probe Queue 2 11 2 1 4 4 Duplicate Dcache Tag Array 2...

Page 4: ... Instructions 2 29 2 9 MAF Memory Address Space Merging Rules 2 30 2 10 Instruction Ordering 2 30 2 11 Replay Traps 2 31 2 11 1 Mbox Order Traps 2 31 2 11 1 1 Load Load Order Trap 2 32 2 11 1 2 Store Load Order Trap 2 32 2 11 2 Other Mbox Replay Traps 2 32 2 12 I O Write Buffer and the WMB Instruction 2 32 2 12 1 Memory Barrier MB WMB TB Fill Flow 2 32 2 12 1 1 MB Instruction Processing 2 33 2 12 ...

Page 5: ...7 1 Probe Commands Four Cycles 4 26 4 7 7 2 Data Transfer Commands Two Cycles 4 28 4 7 8 Data Movement In and Out of the 21264 EV67 4 30 4 7 8 1 21264 EV67 Clock Basics 4 30 4 7 8 2 Fast Data Mode 4 31 4 7 8 3 Fast Data Disable Mode 4 33 4 7 8 4 SysDataInValid_L and SysDataOutValid_L 4 34 4 7 8 5 SysFillValid_L 4 35 4 7 8 6 Data Wrapping 4 36 4 7 9 Nonexistent Memory Processing 4 38 4 7 10 Orderin...

Page 6: ... 5 2 21 Process Context Register PCTX 5 21 5 2 22 Performance Counter Control Register PCTR_CTL 5 23 5 3 Mbox IPRs 5 25 5 3 1 DTB Tag Array Write Registers 0 and 1 DTB_TAG0 DTB_TAG1 5 25 5 3 2 DTB PTE Array Write Registers 0 and 1 DTB_PTE0 DTB_PTE1 5 26 5 3 3 DTB Alternate Processor Mode Register DTB_ALTMODE 5 26 5 3 4 Dstream TB Invalidate All Process ASM 0 Register DTB_IAP 5 27 5 3 5 Dstream TB ...

Page 7: ... 6 10 2 4 Counter Modes for Aggregate Mode 6 20 6 10 3 ProfileMe Mode Programming Guidelines 6 20 6 10 3 1 ProfileMe Mode Precautions 6 20 6 10 3 2 Operation 6 21 6 10 3 3 ProfileMe Counting Mode Description 6 23 6 10 3 3 1 Cycle counting 6 23 6 10 3 3 2 Inum retire delay cycles 6 23 6 10 3 3 3 Retired instructions cycles 6 23 6 10 3 3 4 Bcache miss or long latency probes cycles 6 23 6 10 3 3 5 Mb...

Page 8: ... 8 6 8 8 3 1 Bcache Victim Read During a Dcache Bcache Miss 8 6 8 8 3 2 Bcache Victim Read During an ECB Instruction 8 7 8 9 Memory System Port Single Bit Data Correctable ECC Error 8 7 8 9 1 Icache Fill from Memory 8 7 8 9 2 Dcache Fill from Memory 8 7 8 10 Bcache Data Single Bit Correctable ECC Error on a Probe 8 8 8 11 Double Bit Fill Errors 8 9 8 12 Error Case Summary 8 9 9 Electrical Data 9 1...

Page 9: ...rrupt Code Sequence and STF ITOF D 9 D 6 Restriction 9 PALmode Istream Address Ranges D 10 D 7 Restriction 10 Duplicate IPR Mode Bits D 10 D 8 Restriction 11 Ibox IPR Update Synchronization D 11 D 9 Restriction 12 MFPR of Implicitly Written IPRs EXC_ADDR IVA_FORM and EXC_SUM D 11 D 10 Restriction 13 DTB Fill Flow Collision D 11 D 11 Restriction 14 HW_RET D 11 D 12 Guideline 16 JSR BAD VA D 12 D 13...

Page 10: ...0 Scrubbing a Single Bit Error D 19 D 37 Restriction 41 MTPR ITB_TAG MTPR ITB_PTE Must Be in the Same Fetch Block D 21 D 38 Restriction 42 Updating VA_CTL CC_CTL or CC IPRs D 21 D 39 Restriction 43 No Trappable Instructions Along with HW_MTPR D 21 D 40 Restriction 44 Not Applicable to the 21264 EV67 D 21 D 41 Restriction 45 No HW_JMP or JMP Instructions in PALcode D 21 D 42 Restriction 46 Avoiding...

Page 11: ...M_32 0 5 5 5 6 Virtual Address Format Register VA_48 1 VA_FORM_32 0 5 6 5 7 Virtual Address Format Register VA_48 0 VA_FORM_32 1 5 6 5 8 ITB Tag Array Write Register 5 6 5 9 ITB PTE Array Write Register 5 7 5 10 ITB Invalidate Single Register 5 7 5 11 ProfileMe PC Register 5 8 5 12 Exception Address Register 5 8 5 13 Instruction Virtual Address Format Register VA_48 0 VA_FORM_32 0 5 9 5 14 Instruc...

Page 12: ...ions Flow Example 6 14 6 6 ITB Miss Instructions Flow Example 6 16 7 1 Power Up Timing Sequence 7 3 7 2 Fault Reset Sequence of Operation 7 9 7 3 Sleep Mode Sequence of Operation 7 11 7 4 Example for Initializing Bcache 7 13 7 5 21264 EV67 Reset State Machine State Diagram 7 17 10 1 Type 1 Heat Sink 10 4 10 2 Type 2 Heat Sink 10 5 10 3 Type 3 Heat Sink 10 6 11 1 TAP Controller State Machine 11 4 1...

Page 13: ...64 EV67 Commands 4 10 4 5 System Responses to 21264 EV67 Commands and 21264 EV67 Reactions 4 11 4 6 System Port Pins 4 17 4 7 Programming Values for System Interface Clocks 4 18 4 8 Program Values for Data Sample Drive CSRs 4 18 4 9 Forwarded Clocks and Frame Clock Ratio 4 19 4 10 Bank Interleave on Cache Block Boundary Mode of Operation 4 19 4 11 Page Hit Mode of Operation 4 20 4 12 21264 EV67 to...

Page 14: ...ter Fields 5 21 5 14 Process Context Register Fields Description 5 22 5 15 Performance Counter Control Register Fields Description 5 24 5 16 Performance Counter Control Register Input Select Fields 5 25 5 17 DTB Alternate Processor Mode Register Fields Description 5 27 5 18 Memory Management Status Register Fields Description 5 28 5 19 Mbox Control Register Fields Description 5 30 5 20 Dcache Cont...

Page 15: ...erating Temperature at Heat Sink Center Tc 10 1 10 2 qca at Various Airflows for 21264 EV67 10 2 10 3 Maximum Ta for 21264 EV67 600 MHz and 2 0 V with Various Airflows 10 2 10 4 Maximum Ta for 21264 EV67 667 MHz and 2 0 V with Various Airflows 10 2 10 5 Maximum Ta for 21264 EV67 700 MHz and 2 0 V with Various Airflows 10 2 10 6 Maximum Ta for 21264 EV67 733 MHz and 2 0 V with Various Airflows 10 2...

Page 16: ......

Page 17: ... Interfaces describes the external bus functions and transactions lists bus commands and describes the clock functions Chapter 5 Internal Processor Registers lists and describes the internal processor regis ter set Chapter 6 Privileged Architecture Library Code describes the privileged architecture library code PALcode Chapter 7 Initialization and Configuration describes the initialization and con...

Page 18: ...EV67 and Bcache SSRAMs The Glossary lists and defines terms associated with the 21264 EV67 An Index is provided at the end of the document Documentation Included by Reference The companion volume to this manual the Alpha Architecture Handbook Version 4 con tains the instruction set architecture You can access this document from the following website ftp digital com pub Digital info semiconductor l...

Page 19: ...pixels Abbreviation Meaning IGN Ignore Bits and fields specified are ignored on writes MBZ Must Be Zero Software must never place a nonzero value in bits and fields specified as MBZ A nonzero read produces an Illegal Operand exception Also MBZ fields are reserved for future use RAZ Read As Zero Bits and fields return a zero when read RC Read Clears Bits and fields are cleared when read Unless othe...

Page 20: ...ckets For example 27 specifies bit 27 See also Field Notation Caution Cautions indicate potential damage to equipment or loss of data RW Read Write Bits and fields can be read and written RW n Read Write and takes the value n at power on reset Bits and fields can be read and written W1C Write One to Clear If read operations are allowed to the register then the value may be read by software If it i...

Page 21: ...is indicated by a subscript for example 1002 is a binary number Ranges and Extents Ranges are specified by a pair of numbers separated by two periods and are inclu sive For example a range of integers 0 4 includes the integers 0 1 2 3 and 4 Extents are specified by a pair of numbers in square brackets separated by a colon and are inclusive Bit fields are often specified as extents For example bits...

Page 22: ...truction within implementations Software can never depend on results specified as UNPREDICT ABLE An UNPREDICTABLE result may acquire an arbitrary value subject to a few con straints Such a result may be an arbitrary function of the input operands or of any state information that is accessible to the process in its current access mode UNPREDICTABLE results may be unchanged from their previous value...

Page 23: ...Alpha 21264 EV67 Hardware Reference Manual xxiii X Do not care A capital X represents any valid value ...

Page 24: ......

Page 25: ...s All instructions are 32 bits long Memory operations are either load or store operations All data manipulation is done between registers The Alpha architecture supports the following data types 8 16 32 and 64 bit integers IEEE 32 bit and 64 bit floating point formats VAX architecture 32 bit and 64 bit floating point formats In the Alpha architecture instructions interact with each other only by o...

Page 26: ...es Alpha architecture supports the four integer data types listed in Table 1 1 Note Alpha implementations may impose a significant performance penalty when accessing operands that are not naturally aligned Refer to the Alpha Architecture Handbook Version 4 for details 1 1 3 Floating Point Data Types The 21264 EV67 supports the following floating point data types Longword integer format in floating...

Page 27: ...ns during each CPU clock cycle A peak instruction execution rate of four times the CPU clock frequency An onchip demand paged memory management unit with translation buffer which when used with PALcode can implement a variety of page table structures and trans lation algorithms The unit consists of a 128 entry fully associative data translation buffer DTB and a 128 entry fully associative instruct...

Page 28: ...ammable An internal clock generator providing a high speed clock used by the 21264 EV67 and two clocks for use by the CPU module Onchip performance counters to measure and analyze CPU and system perfor mance Chip and module level test support including an instruction cache test interface to support chip and module level testing A 2 0 V external interface Refer to Chapter 9 for 21264 EV67 dc and ac...

Page 29: ... not intended to be a detailed hardware description of the chip It is organized as follows 21264 EV67 microarchitecture Pipeline organization Instruction issue and retire rules Load instructions to R31 F31 software directed instruction prefetch Special cases of Alpha instruction execution Memory and I O address space Miss address file MAF and load merging rules Instruction ordering Replay traps I ...

Page 30: ...subsections Virtual program counter logic Branch predictor Instruction stream translation buffer ITB Instruction fetch logic Register rename maps Integer and floating point issue queues Exception and interrupt logic Retire logic 2 1 1 1 Virtual Program Counter Logic The virtual program counter VPC logic maintains the virtual addresses for instruc tions that are in flight There can be up to 80 inst...

Page 31: ...IT 0 U0 Integer Registers 1 80 Registers Integer Registers 0 80 Registers Ebox FP ADD DIV SQRT FP MUL FP Registers 72 Registers Fbox Dual Ported Data Cache Physical Address Mbox DTB Dual ported 128 entry Load Queue Store Queue Miss Address File Arbiter Victim Buffer IOWB Duplicate Tag Store Probe Queue Cache Data 128 Cache Index 20 System Bus 64 System Address 15 128 Cbox FP Issue Queue 15 Entries...

Page 32: ...atu rating counter determines the predication taken not taken of the current branch Figure 2 3 Local Predictor Global Predictor The global predictor is indexed by a global history of all recent branches The global predictor correlates the local history of the current branch with all recent branches Fig ure 2 4 shows how the global predictor generates a prediction The global path history is compris...

Page 33: ... 2 5 Choice Predictor 2 1 1 3 Instruction Stream Translation Buffer The Ibox includes a 128 entry fully associative instruction stream translation buffer ITB that is used to store recently used instruction stream Istream address transla tions and page protection information Each of the entries in the ITB can map 1 8 64 or 512 contiguous 8KB pages The allocation scheme is round robin The ITB suppor...

Page 34: ... the control flow predicted by the instruction prefetcher The map logic translates each instruction s operand register specifiers from the virtual register numbers in the instruction to the physical register numbers that hold the corre sponding architecturally correct values The map logic also renames each instruction s destination register specifier from the virtual number in the instruction to a...

Page 35: ...tions can execute in either upper or lower subclusters and are statically assigned before being placed in the IQ The IQ arbiters choose between simultaneous requesters of a subcluster based on the age of the request older requests are given priority over newer requests If a given instruction requests both lower subclusters and no older instruction requests a lower subcluster then the arbiter assig...

Page 36: ...receive pin performance counter overflows and hardware corrected read errors Software interrupts sourced by the software interrupt request SIRR register Asynchronous system traps ASTs Interrupt sources can be individually masked In addition AST interrupts are qualified by the current processor mode 2 1 1 9 Retire Logic The Ibox fetches instructions in program order executes them out of order and t...

Page 37: ...sults for integer add instructions located in U0 U1 L0 and L1 The adders in the lower subclusters that are used to generate the effective virtual address for load and store instructions located in L0 and L1 Four logic units Two barrel shifters and associated byte logic located in U0 and U1 Two sets of conditional branch logic located in U0 and U1 Two copies of an 80 entry register file One pipelin...

Page 38: ...ts are also used for FTOIx instructions 2 1 3 Floating Point Execution Unit The floating point execution unit Fbox has two paths The Fbox executes both VAX and IEEE floating point instructions It support IEEE S_floating point and T_floating point data types and all rounding modes It also supports VAX F_floating point and G_floating point data types and provides limited support for D_floating point...

Page 39: ...fer used for holding Dcache blocks to be written to the Bcache Istream cache blocks from memory to be written to the Bcache Bcache blocks to be written to memory Cache blocks sent to the system in response to probe commands 2 1 4 2 I O Write Buffer The I O write buffer IOWB consists of four 64 byte entries and associated address and control logic used for buffering I O write data between the store...

Page 40: ...uential read and write transaction from and to the same aligned octaword Each Dcache block contains 64 data bytes and associated quadword ECC bits Physical tag bits Valid dirty shared and modified bits Tag parity bit calculated across the tag dirty shared and modified bits One bit to control round robin set allocation one bit per two cache blocks The Dcache contains two sets each with 512 rows con...

Page 41: ...they were fetched from the Icache and places them into the SQ after they are issued by the IQ The SQ holds data associated with store instructions issued from the IQ until they are retired at which point the store can be allowed to update the Dcache The SQ also helps ensure correct Alpha memory reference behavior 2 1 6 3 Miss Address File The 8 entry miss address file MAF holds physical addresses ...

Page 42: ... field the contents of which are applied to the Icache in the next cycle The purpose of the line predictor is to remove the pipe line bubble which would otherwise be created when the branch predictor predicts a branch to be taken In effect the line predictor attempts to predict the Icache line which the branch predictor will generate On fills the line predictor value at each fetch line is initiali...

Page 43: ...he instruction is for the upper or lower subclusters The slot logic makes the decision based on the resources needed by the up to four integer instructions in the fetch block Although all four instructions need not be issued simultaneously distributing their resource usage improves instruction loading across the units For example if a fetch block contains two instructions that can be placed in eit...

Page 44: ...lty as given is measured from the cycle after the fetch stage of the instruction which triggers the abort to the fetch stage of the new target ignoring any Ibox pipeline stalls or queuing delay that the triggering instruction might experience Table 2 1 lists the timing associated with each common source of pipeline abort 2 3 Instruction Issue Rules This section defines instruction classes the func...

Page 45: ...MFPR ibr U0 U1 Integer conditional branch instructions jsr L0 BR BSR JMP CALL RET COR HW_RET CALL_PAL iadd L0 U0 L1 U1 Instructions with opcode 1016 except CMPBGE ilog L0 U0 L1 U1 AND BIC BIS ORNOT XOR EQV CMPBGE ishf U0 U1 Instructions with opcode 1216 cmov L0 U0 L1 U1 Integer CMOV either cluster imul U1 Integer multiply instructions imisc U0 CTLZ CTPOP CTTZ PERR MINxxx MAXxxx PKxx UNPKxx fbr FA ...

Page 46: ...2 in its PC ftoi FST0 FST1 L0 L1 FTOIS FTOIT itof L0 L1 ITOFS ITOFF ITOFT mx_fpcr FM Instructions that move data from the floating point control register Table 2 3 Instruction Group Definitions and Pipeline Unit Instruction Class 3 2 1 0 Slotting 3 2 1 0 Instruction Class 3 2 1 0 Slotting 3 2 1 0 E E E E U L U L L L L L L L L L E E E L U L U L L L L U L L L U E E E U U L L U L L U E L L U U E E L ...

Page 47: ...U L L E U L L U L E E E L U L U U L L L U L LL L E E L L U U L U L L U U L L U L E E U L U L U U L U E U L U L L E L E L U L U U L U L U L U L L E L L L U L L U L U U U L U U L E L U L U L U U U E E U U L L L E U E L U U L U U E L U U L L L E U L L U U L U U E U U U L U L E U U L L U U U U L E U U L L L L E E L L U U U U L L U U L L L L E L L L U L U U L U U U L U L L E U L L U U U U U E U U U L L...

Page 48: ...e latency is greater than 6 cycles fld 4 14 Dcache hit Dcache miss latency with 6 cycle Bcache Add additional Bcache loop latency if Bcache latency is greater than 6 cycles ist Does not produce register value fst Does not produce register value rpcc 1 Possible 1 cycle cross cluster delay rx 1 mxpr 1 or 3 HW_MFPR Ebox IPRs 1 Ibox and Mbox IPRs 3 HW_MTPR does not produce a register value icbr Condit...

Page 49: ...r ftoi Measured from when an fcmov2 is issued from the FQ to when an fst or ftoi is issued from the IQ fdiv 12 9 15 12 Single precision latency to consumer of result value Single precision latency to using divider again Double precision latency to consumer of result value Double precision latency to using divider again fsqrt 18 15 33 30 Single precision latency to consumer of result value Single p...

Page 50: ... result exponent DIVT DIVG EXP 3FF16 OR EXP 216 DIVS DIVF EXP 7F16 OR EXP 38216 2 5 Retire of Operate Instructions into R31 F31 Many instructions that have R31 or F31 as their destination are retired immediately upon decode stage 3 These instructions do not produce a result and are removed from the pipeline as well They do not occupy a slot in the issue queues and do not occupy a functional unit T...

Page 51: ...the operational prefetch behavior of these instructions 2 6 1 Normal Prefetch LDBU LDF LDG LDL LDT LDWU HW_LDL Instructions The 21264 EV67 processes these instructions as normal cache line prefetches If the load instruction hits the Dcache the instruction is dismissed otherwise the addressed cache block is allocated into the Dcache The HW_LDL instruction construct equates to the HW_LD instruction ...

Page 52: ... 6 4 Prefetch with the LDx_L STx_C Instruction Sequence A prefetch within a dynamic 80 instruction window of a LDx_L instruction can cause the subsequent STx_C to incorrectly succeed when all three references are to the same 64 byte cache block Within that 80 instruction window the proximity of the prefetch to the LDx_L instruction directly affects the possibility of the incorrect behavior Fur the...

Page 53: ...h instructions are aborted from the execution pipelines and may request service again in cycle 6 IQ issued instructions are aborted if issued within the speculative window of an integer load instruction that missed in the Dcache even if they are not dependent on the load data However if software misses are likely the 21264 EV67 can still benefit from scheduling the instruction stream for Dcache mi...

Page 54: ...ns a control bit fpWait that when set prevents that entry from asserting its requests This bit is initially set for each floating point store instruction that enters the IQ unless it was the target of a replay trap The instruction s FQ clone is issued when its Ra register is about to become clean resulting in its IQ clone s fpWait bit being cleared and allowing the IQ clone to issue and be execute...

Page 55: ...es floating point CMOV instructions as two distinct 4 cycle latency operations 2 8 Memory and I O Address Space Instructions This section provides an overview of the way the 21264 EV67 processes memory and I O address space instructions The 21264 EV67 supports and internally recognizes a 44 bit physical address space that is divided equally between memory address space and I O address space Memory...

Page 56: ...h by attempting to merge I O load instructions in a merge register Table 2 7 shows the rules for merging data The columns represent the load instructions replayed to the MAF while the rows represent the size of the load in the merge register In summary Table 2 7 shows some of the following rules Byte word load instructions and different size load instructions are not allowed to merge A stream of a...

Page 57: ... SQ entries have been transferred into the Dcache This restriction assists in STx_C instruction and Dcache ECC processing SQ entry data that has not been transferred to the Dcache may source data to newer load instructions The Mbox compares the virtual Dcache index bits of incoming load instructions to queued SQ entries and sources the data from the SQ bypassing the Dcache when necessary 2 8 4 I O...

Page 58: ... has closed its merge window the Cbox sends I O space store requests offchip in the order that they were received from the Mbox 2 9 MAF Memory Address Space Merging Rules Because all memory transactions are to 64 byte blocks efficiency is improved by merg ing several small data transactions into a single larger data transaction Table 2 9 lists the rules the 21264 EV67 uses when merging memory tran...

Page 59: ...Mbox uses replay traps to manage the memory stream are load load and store load order traps Table 2 10 Memory Reference Ordering First Instruction in Pair Second Instruction In Pair Reference Order Load memory to address X Load memory to address X Maintained litmus test 1 Load memory to address X Load memory to address Y Not maintained Store memory to address X Store memory to address X Maintained...

Page 60: ...instruction The stWait table produces 1 bit for each instruction accessed from the Icache When a load instruction gets a store load order replay trap its associated bit in the stWait table is set during the cycle that the load is refetched Hence the trapping load instruction s stWait bit will be set the next time it is fetched The IQ will not issue load instructions whose stWait bit is set while t...

Page 61: ...rol of instruction flow is based upon the value in Cbox CSR SYSBUS_MB_ENABLE as follows If Cbox CSR SYSBUS_MB_ENABLE is clear the Cbox waits until the IQ is empty and then performs the following actions a Sends all pending MAF and IOWB entries to the system port b Monitors Cbox CSR MB_CNT 3 0 a 4 bit counter of outstanding committed events When the counter decrements from one to zero the Cbox mark...

Page 62: ...s the youngest probe queue entry c When a probe response has been sent to the system for the marked probe queue entry the Cbox considers the WMB to be satisfied If Cbox CSR SYSBUS_MB_ENABLE is set the Cbox performs the following actions a Stalls further MAF and IOWB processing b Sends the MB command to the system port c Waits until the MB command is acknowledged by the system with a SysDc MBDone c...

Page 63: ... Cbox completes processing the MB instruction using one of the above sequences depending upon the state of SYSBUS_MB_ENABLE the Cbox sig nals the Ibox to clear IPR scoreboard bit 0 The 21264 EV67 uses a similar mechanism to process Istream TB misses and fills to the PTE for the Istream 1 The integer queue issues a HW_LD instruction with VPTE 2 The IQ issues a HW_MTPR instruction with an ITB_PTE th...

Page 64: ...methods use the same hardware registers See Section 6 10 for information about counter control 2 14 Floating Point Control Register The floating point control register FPCR is shown in Figure 2 11 Figure 2 11 Floating Point Control Register The floating point control register fields are described in Table 2 14 Table 2 14 Floating Point Control Register Fields Name Extent Type Description SUM 63 RW...

Page 65: ... the destination exponent DZE 53 RW Divide by zero An attempt was made to perform a floating point divide with a divisor of zero INV 52 RW Invalid operation An attempt was made to perform a floating point arithmetic operation and one or more of its operand values were illegal OVFD 51 RW Overflow disable If this bit is set and a floating point arithmetic operation gen erates an overflow condition t...

Page 66: ...1264 EV67 Table 2 15 21264 EV67 AMASK Values 21264 EV67 Pass Level AMASK Feature Mask Value See I_CTL CHIP_ID Table 5 11 30716 Table 2 16 AMASK Bit Assignments Bit Meaning 0 Support for the byte word extension BWX The instructions that comprise the BWX extension are LDBU LDWU SEXTB SEXTW STB and STW 1 Support for the square root and floating point convert extension FIX The instructions that compri...

Page 67: ... sys tem configuration could be used in standalone or networked workstations Figure 2 12 Typical Uniprocessor Configuration Figure 2 13 shows a typical multiprocessor system each processor with a second level cache Each interface controller must employ a duplicate tag store to maintain cache coherency This system configuration could be used in a networked database server application 21264 Tag Addr...

Page 68: ...Examples Figure 2 13 Typical Multiprocessor Configuration 64 bit PCI Bus 64 bit PCI Bus 21264 L2 Cache 21264 L2 Cache 21272 Core Logic Chipset Control Chip Data Slice Chips Host PCI Bridge Chip Host PCI Bridge Chip DRAM Arrays Address Data DRAM Arrays Address Data FM 05574 EV67 ...

Page 69: ...is chapter also describes the mechanical specifications of the 21264 EV67 It is organized as follows The 21264 EV67 logic symbol The 21264 EV67 signal names and functions Lists of the signal pins sorted by name and PGA location The specifications for the 21264 EV67 mechanical package The top and bottom views of the 21264 EV67 pinouts 3 1 21264 EV67 Microprocessor Logic Symbol Figure 3 1 show the l...

Page 70: ...7 0 SysDataOutClk_L 7 0 SysDataInValid_L SysDataOutValid_L SysFillValid_L BcAdd_H 23 4 BcData_H 127 0 BcCheck_H 15 0 BcDataInClk_H 7 0 BcDataOutClk_ 3 0 BcDataOE_L BcDataWr_L BcTag_H 42 20 BcTagInClk_H BcTagOutClk_x BcVref BcTagDirty_H BcTagParity_H BcTagShared_H BcTagValid_H BcTagOE_L BcTagWr_L BcLoad_L x Clocks ClkIn_x FrameClk_x EV6Clk_x PLL_VDD Miscellaneous IRQ_H 5 0 ClkFwdRst_H SromData_H Tm...

Page 71: ...erential amplifier receiver with open drain output B_DA_PP Bidirectional differential amplifier receiver with push pull output Other Spare Reserved to Compaq1 1 All Spare connections are Reserved to Compaq to maintain compatibility between passes of the chip Designers should not use these pins NoConnect No connection Do not connect to these pins for any revision of the 21264 EV67 These pins must f...

Page 72: ...orward receive circuits similar to the system interface BcTagOE_L O_PP 1 Bcache tag output enable This signal is asserted by the 21264 EV67 for Bcache read operations BcTagOutClk_H BcTagOutClk_L O_PP 2 Bcache tag output clock These clocks echo the clock for warded BcDataOutClk_x 3 0 clocks BcTagParity_H B_DA_PP 1 Tag parity state bit BcTagShared_H B_DA_PP 1 Tag shared state bit The 21264 EV67 will...

Page 73: ...cle time of the GCLK internal 21264 EV67 clock SromData_H I_DA 1 Serial ROM data Input data line from the SROM SromOE_L O_OD_TP 1 Serial ROM enable Supplies the output enable to the SROM SysAddIn_L 14 0 I_DA 15 Time multiplexed command address ID Ack from system to the 21264 EV67 SysAddInClk_L I_DA 1 Single ended forwarded clock from system for SysAddIn_L 14 0 and SysFillValid_L SysAddOut_L 14 0 O...

Page 74: ...E 1149 1 test mode select signal Trst_L I_DA 1 IEEE 1149 1 test access port TAP reset signal Table 3 3 21264 EV67 Signal Descriptions by Function Signal Type Count Description BcVref Domain BcAdd_H 23 4 O_PP 20 Bcache index BcCheck_H 15 0 B_DA_PP 16 ECC check bits for BcData_H 127 0 BcData_H 127 0 B_DA_PP 128 Bcache data BcDataInClk_H 7 0 I_DA 8 Bcache data input clocks BcDataOE_L O_PP 1 Bcache da...

Page 75: ...iven in previous SysDC command SysVref I_DC_REF 1 System interface reference voltage Clocks and PLL ClkIn_H ClkIn_L I_DA_CLK 2 Differential input signals provided by the system EV6Clk_H EV6Clk_L O_PP_CLK 2 Provides an external test point to measure phase alignment of the PLL FrameClk_H FrameClk_L I_DA_CLK 2 A skew controlled differential 50 duty cycle copy of the system clock It is used by the 212...

Page 76: ...P 1 IEEE 1149 1 test data out signal TestStat_H O_OD_TP 1 Test status pin Tms_H I_DA 1 IEEE 1149 1 test mode select signal Trst_L I_DA 1 IEEE 1149 1 test access port TAP reset signal Table 3 4 Pin List Sorted by Signal Name Signal Name PGA Location Signal Name PGA Location Signal Name PGALocation BcAdd_H_10 B30 BcAdd_H_11 D30 BcAdd_H_12 C31 BcAdd_H_13 H28 BcAdd_H_14 G29 BcAdd_H_15 A33 BcAdd_H_16 E...

Page 77: ...40 BcData_H_35 C41 BcData_H_36 C43 BcData_H_37 E43 BcData_H_38 G41 BcData_H_39 F44 BcData_H_4 C3 BcData_H_40 K44 BcData_H_41 N41 BcData_H_42 M44 BcData_H_43 P42 BcData_H_44 U43 BcData_H_45 V44 BcData_H_46 Y42 BcData_H_47 AB44 BcData_H_48 AD42 BcData_H_49 AE43 BcData_H_5 E3 BcData_H_50 AF42 BcData_H_51 AJ45 BcData_H_52 AK42 BcData_H_53 AN45 BcData_H_54 AP44 BcData_H_55 AN41 BcData_H_56 AW45 BcData_...

Page 78: ...ag_H_34 E19 BcTag_H_35 B18 BcTag_H_36 A19 BcTag_H_37 F20 BcTag_H_38 D20 BcTag_H_39 E21 BcTag_H_40 C21 BcTag_H_41 D22 BcTag_H_42 H22 BcTagDirty_H C23 BcTagInClk_H G19 BcTagOE_L H24 BcTagOutClk_H C25 BcTagOutClk_L D24 BcTagParity_H B22 BcTagShared_H G23 BcTagValid_H B24 BcTagWr_L E25 BcVref F18 ClkFwdRst_H BE11 ClkIn_H AM8 ClkIn_L AN7 DCOK_H AY18 EV6Clk_H AM6 EV6Clk_L AL7 FrameClk_H AV16 FrameClk_L ...

Page 79: ...Data_L_27 AV6 SysData_L_28 AV10 SysData_L_29 AW11 SysData_L_3 H12 SysData_L_30 AV12 SysData_L_31 AW13 SysData_L_32 F32 SysData_L_33 F34 SysData_L_34 H34 SysData_L_35 G35 SysData_L_36 F40 SysData_L_37 G39 SysData_L_38 K38 SysData_L_39 J41 SysData_L_4 H10 SysData_L_40 M40 SysData_L_41 N39 SysData_L_42 P40 SysData_L_43 T38 SysData_L_44 V40 SysData_L_45 W41 SysData_L_46 W39 SysData_L_47 Y40 SysData_L_...

Page 80: ...17 AD38 SysData_L_50 AD4 BcData_H_82 AD42 BcData_H_48 AD44 BcData_H_113 AD8 SysData_L_18 AE3 BcData_H_18 AE41 BcData_H_114 AE43 BcData_H_49 AE5 SysData_L_19 AF4 BcData_H_83 AF40 SysData_L_51 AF42 BcData_H_50 AF6 SysDataInClk_H_2 AG1 BcData_H_19 AG41 SysDataInClk_H_6 AG45 BcData_H_115 AG7 SysDataOutClk_L_2 AH2 BcDataInClk_H_2 AH38 SysData_L_52 AH40 SysDataOutClk_L_6 AH44 BcDataInClk_H_6 AH6 SysData...

Page 81: ...20 Trst_L AY26 SysAddIn_L_8 AY28 SysAddIn_L_2 AY32 SysAddOut_L_5 AY34 SysCheck_L_7 AY38 SysData_L_60 AY40 BcDataInClk_H_7 AY44 BcData_H_58 AY6 SysDataInClk_H_3 AY8 SysDataOutClk_L_3 B10 BcData_H_0 B12 BcTag_H_23 B16 BcTag_H_31 B18 BcTag_H_35 B22 BcTagParity_H B24 BcTagValid_H B28 BcAdd_H_4 B30 BcAdd_H_10 B34 BcAdd_H_18 B36 BcAdd_H_20 B4 BcData_H_68 B40 BcData_H_34 B42 BcData_H_99 B6 BcData_H_67 BA...

Page 82: ...Add_H_12 C35 BcAdd_H_22 C37 BcData_H_33 C41 BcData_H_35 C43 BcData_H_36 C5 BcData_H_3 C9 BcData_H_66 D10 BcData_H_1 D14 BcTag_H_24 D16 BcTag_H_30 D2 BcData_H_71 D20 BcTag_H_38 D22 BcTag_H_41 D24 BcTagOutClk_L D26 BcDataWr_L D30 BcAdd_H_11 D32 BcAdd_H_17 D36 BcData_H_97 D4 BcData_H_69 D42 BcData_H_100 D44 BcData_H_101 D8 SysDataInClk_H_0 E1 BcData_H_7 E13 BcTag_H_20 E15 BcTag_H_25 E19 BcTag_H_34 E2...

Page 83: ...a_H_11 M38 BcCheck_H_4 M40 SysData_L_40 M44 BcData_H_42 M6 SysData_L_8 M8 BcCheck_H_8 N1 BcData_H_76 N39 SysData_L_41 N41 BcData_H_41 N45 BcData_H_107 N5 BcData_H_74 N7 SysData_L_9 P4 SysDataInClk_H_1 P40 SysData_L_42 P42 BcData_H_43 P6 SysData_L_10 R3 BcDataInClk_H_1 R41 SysDataOutClk_L_5 R43 SysDataInClk_H_5 T2 BcData_H_12 T38 SysData_L_43 T4 Spare T44 BcData_H_108 T8 SysData_L_11 U1 BcData_H_13...

Page 84: ...3 BA29 BA35 BA41 BA5 BA7 BC1 BC13 BC19 BC27 BC33 BC39 BC45 BC7 BE15 BE21 BE25 BE3 BE31 BE37 BE43 C1 C13 C19 C27 C33 C39 C45 C7 DS8 E11 E17 E23 E29 E35 E41 E5 E9 G15 G21 G25 G3 G31 G37 G43 G9 J1 J39 J45 J7 L41 L5 N3 N43 R1 R39 R45 R5 R7 T42 U41 U5 W3 W43 VDD A23 AB40 AB6 AD40 AD6 AF2 AF38 AF44 AF8 AH4 AH42 AK40 AK6 AM2 AM38 AM44 AP4 AP42 AP6 AT40 AT6 AV14 AV2 AV20 AV26 AV32 AV38 AV44 AY10 AY16 AY22...

Page 85: ...x Lid FM 05662 AI4 2 54 mm 100 in Typ 587x 1 40 mm 055 in Typ 1 27 mm 050 in Typ 27 94 mm 1 100 in 27 94 mm 1 100 in 59 94 mm 2 360 in Typ 29 62 mm 1 180 in Typ 25 40 mm 1 000 in Typ 53 85 mm 2 120 in Typ 1 27 mm 050 in Typ 4 32 mm 170 in Typ 1 377 mm 055 in Typ 13 mm 005 in R 7 62 mm 300 in Typ 1 905 mm 075 in Typ 29 62 mm 1 180 in Typ BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD A...

Page 86: ...p view with pins facing down Figure 3 3 21264 EV67 Top View Pin Down FM 05644 EV67 BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 01 03 05 07 09 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 08 06 04 02 21264 EV67 Top View PinDown BC 45 44 BE BD B ...

Page 87: ... pins facing up Figure 3 4 21264 EV67 Bottom View Pin Up FM 05645 EV67 BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 09 07 05 03 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 21264 EV67 BottomView PinUp BC 01 02 BE BD B ...

Page 88: ......

Page 89: ...efines all 21264 EV67 hardware interface signal pins Chapter 9 describes the 21264 EV67 hardware interface electrical requirements 4 1 Introduction to the External Interfaces A 21264 EV67 based system can be divided into three major sections 21264 EV67 microprocessor Second level Bcache System interface logic Optional duplicate tag store Optional lock register Optional victim buffers The 21264 EV6...

Page 90: ...3 0 clocks around and returns them to the 21264 EV67 as BcDataInClk_H 7 0 Likewise BcTagOutClk_x returns as BcTagInClk_H The Bcache interface supports a 64 byte block size The system interface includes a 64 bit bidirectional data bus two 15 bit unidirectional address buses and several control signals The SysAddOutClk_L clock is free running and is derived from the internal GCLK The period of SysAd...

Page 91: ...ontrol pins The 15 bit address buses provide time shared address command ID in two or four GCLK cycles The Cbox controls the system interface BcData_H 127 0 BcAdd_H 23 4 BcCheck_H 15 0 BcDataInClk_H 7 0 BcDataOutClk_x 3 0 BcDataOE_L BcDataWr_L 21264 SysAddOut_L 14 0 SysAddInClk_L SysAddIn_L 14 0 SysAddOutClk_L SysVref FM 05818B EV67 SysDataInClk_H 7 0 SysCheck_L 7 0 SysData_L 63 0 SysDataOutClk_L ...

Page 92: ...f 5 6 7 and 8 times the CPU clock cycle The 1 5 multi ple is only available in dual data mode 4 2 Physical Address Considerations The 21264 EV67 supports a 44 bit physical address space that is divided equally between memory space and I O space Memory space resides in the lower half of the physical address space PA 43 0 and I O space resides in the upper half of the phys ical address space PA 43 1...

Page 93: ...emory 1 1 X X Store Dcache hit and writable done STx Memory 1 0 X X Store hit and not writable set dirty flow note 1 STx Memory 0 X 1 1 Store Bcache hit and writable done STx Memory 0 X 1 0 Store hit and not writable set dirty flow note 1 STx Memory 0 X 0 X Miss generate RdBlkMod command STx I O X X X X WrBytes WrLWs or WrQWs based on size STx_C Memory 0 X X X Fail STx_C STx_C Memory 1 0 X X STx_C...

Page 94: ... EV67 issues an Evict command on the system interface only if a Bcache index match to the ECB address is found in the 21264 EV67 cache system Note that whenever ENABLE_EVICT 0 is true in the write many chain BC_CLEAN_VICTIM must also be true in the write once chain Otherwise the 21264 EV67 could respond miss to a probe rather than hit before an Evict command has been sent off chip but after the Ev...

Page 95: ... times the CPU clock cycle The 1 5 multiple is only available in dual data mode 4 3 1 Bcache Interface Signals Figure 4 2 shows the 21264 EV67 system interface signals Figure 4 2 21264 EV67 Bcache Interface Signals 4 3 2 System Duplicate Tag Stores The 21264 EV67 provides Bcache state support for systems with and without duplicate tag stores and will take different actions on this basis The system...

Page 96: ...Blk command optional assigns and uses a VDB Each VDB has two valid bits that indicate the buffer is valid for a victim or valid for a probe or valid for both a victim and a probe Probe commands that match the address of a victim address file VAF entry with an asserted probe valid bit P will stall the 21264 EV67 probe queue No ProbeResponses will be returned until the P bit is clear The release vic...

Page 97: ...uires the system to allow only one change to a block at a time This means that if the 21264 EV67 gains the bus to read or write a block no other node on the bus should be allowed to access that block until the data has been moved The 21264 EV67 provides hardware mechanisms to support several cache coher ency protocols The protocols can be separated into two classes write invalidate cache coherency...

Page 98: ... for DMA transactions that sample data but do not want to update tag state Clean Independent of previous state update next state to Clean Clean Shared Independent of previous state update next state to Clean Shared This transac tion is useful for systems that update memory on probe hits T1 Clean Clean Shared Dirty Dirty Shared Based on the dirty bit make the block clean or dirty shared This transa...

Page 99: ...in the 21264 EV67 cache system FetchBlk and FetchBlkSpec are noncached references to memory space that have missed in the 21264 EV67 cache system Rdiox commands are noncached references to I O address space Evict and STCChangeToDirty commands are generated by ECB and STx_C instructions respectively Table 4 5 shows the system responses to 21264 EV67 commands and 21264 EV67 reactions Table 4 5 Syste...

Page 100: ...64 EV67 to generate a victim for this block upon eviction ChxToDirty ReadDataDirty The data in the Dcache is replaced with the filled data The block is writable so the store instruction that generated the original command can update this block Any STx_C instruction to this block is forced to fail In addition the 21264 EV67 generates a victim for this block upon eviction ChxToDirty ReadDataError Im...

Page 101: ...nowledge of the bits function is useful to programmers optimizing the scheduling of the Bcache data bus The Cbox contains a duplicate copy of the Dcache tag array In contrast to the Dcache tag array DTAG which is virtually indexed the Cbox copy of the Dcache tag array CTAG is physically indexed The Cbox uses the CTAG array entries in the following situations InvalToDirty ChangeToDirtyFail Illegal ...

Page 102: ...struction processing in the processor core 4 6 Lock Mechanism The 21264 EV67 does not contain a dedicated lock register nor are system components required to do so When a load lock LDx_L instruction executes data is accessed from the Dcache or Bcache If there is a cache miss data is accessed from memory with a RdBlk command Its associated cache line is filled into the Dcache in the clean state if ...

Page 103: ...ces between LDx_L STx_C pairs To prevent load or store instructions older than the LDx_L from evicting the LDx_L cache block the Mbox invokes a replay trap on the incoming load or store instruction which also aborts the LDx_L These instructions are issued in program order in the next iteration of the trap retry down the pipeline To prevent newer load or store instructions from evicting the locked ...

Page 104: ...an be set to place the 21264 EV67 in full time conservative mode M_CTL SMC can be set to place the 21264 EV67 in periodic conservative mode timed by two counters an 8 bit primary counter that tracks branch mispredicts and conditional branch retires and a backup counter that places the 21264 EV67 in conservative mode for a period of 16K cycles every 2 million cycles The 8 bit counter is enabled by ...

Page 105: ...L O_OD 1 Single ended forwarded clock SysVref I_DC_REF 1 System interface reference voltage SysCheck_L 7 0 B_DA_OD 8 Quadword ECC check bits for SysData_L 63 0 SysData_L 63 0 B_DA_OD 64 Data bus for memory and I O data SysDataInClk_H 7 0 I_DA 8 Single ended system generated clocks for clock forwarded input system data SysDataInValid_L I_DA 1 When asserted marks a valid data cycle for data transfer...

Page 106: ... In Table 4 8 each system forwarded clock is the inversion of the low assertion signal at the corresponding pin Table 4 7 Programming Values for System Interface Clocks System Transfer SYS_CLK_LD_VECTOR1 1 These are hexadecimal values SYS_BPHASE_LD_VECTOR1 SYS_FDBK_EN1 1 5X DD 9249 5 02 2 0X DD 3333 0 01 2 5X DD 8C63 5 02 3 0X DD 71C7 0 10 3 5X DD C387 A 04 4 0X DD 0F0F 0 01 5 0X DD 7C1F 0 40 6 0X...

Page 107: ...ry bank and drive the RAS address as soon as possible 4 7 3 1 Bank Interleave on Cache Block Boundary Mode Table 4 10 shows the command format for the bank interleave on cache block bound ary mode of operation 21264 EV67 to system SYS_DDM_RD_RISE_EN 0 Enables the sampling of incoming data on the rising edge of the incoming forwarded clock Always asserted SYS_DDMF_ENABLE Enables the falling edge of...

Page 108: ...13 bit command address field M2 When set reports that the oldest probe has missed in cache Also this bit is set for system to 21264 EV67 probe commands that hit but have no data movement see the CH bit below When clear has no meaning M1 and M2 are not asserted simultaneously Reporting probe results as soon as possible is critical to high speed operation so when a result is known the 21264 EV67 use...

Page 109: ...erleave full address 0 01 36 Bank interleave SysAddOut_L 0 unused 0 10 Illegal Illegal combination 0 11 34 Bank interleave both SysAddOut_L 1 0 are used for I O 1 00 38 Page hit mode full address 1 01 36 Page hit mode SysAddOut_L 0 unused 1 10 Illegal Illegal combination 1 11 34 Page hit mode both SysAddOut_L 1 0 are unused Table 4 14 21264 EV67 to System Commands Descriptions Command Command 4 0 ...

Page 110: ...imBlk 00101 Address of a clean victim optional Evict4 00110 Invalidate evicted block at the given Bcache index optional ReadBytes 01000 I O read byte mask ReadLWs 01001 I O read longword mask ReadQWs 01010 I O read quadword mask WrBytes 01100 I O write byte mask WrLWs 01101 I O write longword mask WrQWs 01110 I O write quadword mask CleanToDirty6 11100 Sets a block dirty that was previously clean ...

Page 111: ...ctimBlk commands are enabled they immediately follow RdBlkVic RdBlkModVic and InvalToDirtyVic commands 4 Systems can optionally enable Evict commands by asserting the Cbox CSR ENABLE_EVICT In this mode all ECB instructions will generate an Evict com mand and in combination with BC_RDVICTIM 0 mode the WriteVictim or CleanVictim when Cbox CSR BC_CLEAN_VICTIM 0 is asserted is associated with the Evic...

Page 112: ...fer on SysAddOut_L 14 0 As shown in Table 4 14 the Command 4 0 field for a ProbeRe sponse command equals 00001 Table 4 17 shows the format of the 21264 EV67 Prob eResponse command Table 4 16 Programming SET_DIRTY_ENABLE 2 0 SET_DIRTY_ENABLE 2 0 DS CS C Cbox Action 000 Everything acknowledged internally uniprocessor 001 Only clean blocks generate external acknowledge CleanToDirty commands only 010 ...

Page 113: ...c command The 21264 EV67 stops sending new commands when the counter hits the maxi mum count specified by Cbox CSR SYSBUS_ACK_LIMIT 4 0 When this counter is programmed to zero the CMD_ACK count is ignored unlimited com mands are allowed in flight Because RdBlkxVic and WrVictimBlk commands are atomic when the CSR BC_RDVICTIM 0 is set the 21264 EV67 does not send a RdBlkxVic command if the SYSBUS_AC...

Page 114: ...rating victim commands on the system port Because victim and read commands are atomic when BC_RDVICTIM 0 1 the RdBlkxVic commands are stalled when the victim limit is reached Programming the SYSBUS_VIC_LIMIT 2 0 to zero disables this limit 4 7 7 System to 21264 EV67 Commands The system can send either probes 4 cycle or data movement 2 cycle commands to the 21264 EV67 Signal pin SysAddIn_L 14 in th...

Page 115: ...r IOWB valid bit specified in ID 3 0 RPB Clears probe valid bit specified in ID 2 0 A Command acknowledge When set the 21264 EV67 decrements its command outstand ing counter SYSBUS_ACK_LIMIT 4 0 ID 3 0 Identifies the victim data buffer VDB number or the I O write buffer IOWB number Bit 3 is only asserted for the IOWB C Commit bit This bit decrements the uncommitted event counter MB_CNTR used for M...

Page 116: ...formed to the host processor 4 7 7 2 Data Transfer Commands Two Cycles Data transfer commands use a 2 cycle format on SysAddIn_L 14 0 The SysDc 4 0 field indicates success or failure for ChangeToDirty and MB commands and error con ditions as shown in Table 4 24 The pattern of data is controlled by the SysDataInValid_L and SysDataOutValid_L signals These signals are valid each cycle of data transfe...

Page 117: ...1264 EV67 ReadDataError 00001 Data is returned for read commands The system drives the SysData bus I O or memory NXM ChangeToDirtySuccess 00100 No data SysData is ignored by the 21264 EV67 This command is also used for the InvalToDirty response ChangeToDirtyFail 00101 No data SysData is ignored by the 21264 EV67 This command is also used for the Evict response MBDone 00110 Memory barrier operation...

Page 118: ...67 uses a clock forwarding technique to achieve very high bandwidth on its pin interfaces The clock forwarding technique has three main principles 1 Local point to point transfers can be made safely and at very high bandwidth if the sender can provide the receiver with a forward clock FWD_CLK to latch the transmitted data at the receiver The SysAddOutClk_L and SysDataOutClk_L 7 0 pins provide the ...

Page 119: ... point in time which will be referred to as the point the command is perceived by 21264 EV67 4 7 8 2 Fast Data Mode The 21264 EV67 is the default driver of the bidirectional SysData bus1 As the 21264 EV67 is processing WrVictim ProbeResponse only the hit case and IOWB com mands to the system accompanying data is made available at the clock forwarded bus Because there is a bandwidth difference betw...

Page 120: ... command the 21264 EV67 turns off its drivers interrupting any ongoing fast data write transactions 2 The 21264 EV67 drivers stay off until the last piece of fill data is received or a new SysDc write command overrides the current SysDc fill command It is the responsi bility of the external system to schedule SysDc fill or write commands so that there is no conflict on the SysData bus 3 The 21264 ...

Page 121: ...4 7 8 3 Fast Data Disable Mode The system controls all data movement to and from the 21264 EV67 Movement of data into and out of the 21264 EV67 is preceded by a SysDc command The 21264 EV67 drivers are only enabled for the duration of an 8 cycle transfer of data from the 21264 EV67 to the system Systems must ensure that there is no overlap of enabled drivers and that there is adequate settle time ...

Page 122: ...ional delay of one bit time 1 5 GCLKs puts the actual delay after perceiv ing the SysDc command to 7 5 GCLKS which misses the 8 5 cycle constraint There fore the 21264 EV67 drives data two SYSCLKs after receiving the SysDc write command For system 2 the distance between SysDc and the second SYSCLK is eight GCLK cycles which also misses the 8 5 cycle constraint so the 21264 EV67 drives data three S...

Page 123: ...as a SYSDC_DELAY of five GCLKs Running at a bit time of 1 5X the DATA_VALID_DELAY 1 0 is pro grammed with a value of three SysDataOutValid_L Systems that use a ratio of 1 1 for SYSCLK INT_FWD_CLK may control the flow of data out of the 21264 EV67 by using SysDataOutValid_L as follows 1 The SysDataOutValid_L pin must be asserted for at least the first cycle of the SysDc write command that initiates...

Page 124: ... to reflect back the same low order address bits and the cor responding octaword found in the SysAddOut field or the system chooses any other starting point within the block SysDc commands for the ReadData ReadDataShared and WriteData groups require that systems define the position of the first QW by inserting the appropriate value of SysAddOut_L 5 3 into bits 1 0 of the command field The recommen...

Page 125: ...he system again may elect to choose its own starting point for the transfer and insert that value into SysDc 1 0 See Table 4 31 for the wrap order Table 4 30 defines the interleaved scheme for the wrap order Table 4 29 System Wrap and Deliver Data Source Destination SysDc 4 2 SysDc 1 0 Size Rules Memory 100 ReadData SysAddOut_L 5 4 Block 64 Bytes See Note 1 Memory 101 ReadDataDirty SysAddOut_L 5 4...

Page 126: ... speculative references instruction execution down mispre dicted paths to NXM space In these cases the system sends a SysDc ReadDataError and the 21264 EV67 does the following Delivers an all ones pattern to all load instructions to the NXM address Force fails all store instructions to the NXM address much like a STx_C failure Invalidates the cache block at the same index by way of an atomic Evict...

Page 127: ...start instruction processing down the correctly pre dicted path If the reference was not speculative there must be an error in the operating system mapping of a virtual address to an illegal physical address and the 21264 EV67 provides an all ones pattern as a signature for this bug The NXM block is not cached in the Bcache but can be cached in the Icache RdBlkMod RdBlkModSpec RdBlkModVic Store in...

Page 128: ...er when issu ing release buffer commands Probe processing can stall inside the 21264 EV67 when the probe entry index matches PA 19 6 of a previous probe entry in the VAF The 21264 EV67 reserves one VAF entry for probe processing so that VAF full conditions cannot stall the processing of probes at the head of the queue Table 4 33 lists all interactions between pending internal 21264 EV67 commands a...

Page 129: ...sor This race condition can be managed by either forcing the completion of the WrVictimBlk command to memory before allowing the progress by the probing processor or by killing the WrVictimBlk command in this processor CleanToDirty SharedToDirty This case assumes that a SetDirty command has been sent to the system environment because of a store instruction that hit in the 21264 EV67 caches and tha...

Page 130: ...g the SysDc MAF command to the 21264 EV67 To ensure that a probe updates a VAF entry before a SysDc VAF release buffer systems must wait for the probe response Probe SysDc VAF Same as Probe SysDc MAF above SysDc MAF Probe To ensure that a SysDc MAF command updates the 21264 EV67 cache system before a probe to the same address systems must deliver the D1 the second QW of data delivered to the 21264...

Page 131: ...nal types referred to in this section Table 4 36 lists the Bcache port pin groups along with their type number reference clock and functional description Table 4 35 Range of Maximum Bcache Clock Ratios SYSCLK Ratio Bcache Clock Ratio with Fast Mode Enabled Bcache Clock Ratio with Fast Mode Disabled 1 5X 4 0X 7 0X 2 0X 4 0X 7 0X 2 5X 5 0X 8 0X 3 0X 6 0X 8 0X 3 5X 7 0X 8 0X 4 0X 7 0X 8 0X 5 0X 8 0X ...

Page 132: ...data pins are BcCheck_H 15 0 BcData_H 127 0 BcTag_H 42 20 BcTagDirty_H BcTagParity_H BcDataWr_L O_PP 1 Int_Index_BcClk Bcache data write enable BcLoad_L O_PP 1 Int_Index_BcClk Bcache burst enable BcTag_H 42 20 B_DA_PP 23 Int_Data_BcClk output BcTagInClk_H input Bcache tag data BcTagDirty_H B_DA_PP 1 Int_Data_BcClk output BcTagInClk_H input Bcache tag dirty bit BcTagInClk_H I_DA 1 NA Tag input data...

Page 133: ...the index and clock pins by using Cbox CSRs BC_CPU_CLK_DELAY 1 0 and BC_CLK_DELAY 1 0 Table 4 38 provides the BC_CLK_DELAY 1 0 values which is the delay from BC_WRITE_DATA to BC_CLOCK_OUT in GCLK phases With BC_CPU_CLK_DELAY 1 0 and BC_CLK_DELAY 1 0 a 500 MHz 21264 EV67 can provide up to 8 ns 3 2 2 of delay between the index and the outgoing forwarded clocks The relative loading difference between...

Page 134: ...at is high for three GCLK phases and low for four GCLK phases Also for both of these cases the 21264 EV67 will only start transactions on the rising edge of the GCLK and the Bcache clock The 1 5X SD case is not supported A dual data rate DDR SSRAM s data rate is derived in a similar manner except that because both edges of the clock are used the SSRAM clock generated is 2X the period of the data T...

Page 135: ...rive Cbox CSRs CBOX CSR Description BC_DDM_FALL_EN 0 Enables the update of the 21264 EV67 s Bcache outputs referenced to the falling edge of the Bcache forwarded clock Dual data RAMs assert this CSR BC_TAG_DDM_FALL_EN 0 Enables the update of the 21264 EV67 s Bcache tag outputs referenced to the falling edge of the Bcache forwarded clock Alway deasserted BC_DDM_RISE_EN 0 Enables the update of the 2...

Page 136: ...om of the shift register the processor samples the Bcache data and delivers it to the consumers of load data in the 21264 EV67 functional units For example when a 2 5X SD SSRAM has a latency of eight GCLK cycles from BcAdd_H 23 4 to the output of Bcache FIFO Cbox CSR BC_LAT_DATA_PATTERN 31 0 is programmed to 94816 and Cbox CSR BC_LAT_TAG_PATTERN 23 0 is programmed to 816 The data pattern contains ...

Page 137: ...tup for the data at the Bcache data flip flop 4 For Bcache writes the 21264 EV67 drivers are enabled on the GCLK BPHASE preceding the start of a write transfer and disabled on the succeeding GCLK BPHASE at the end of a write transfer Thus the write data is enveloped by the 21264 EV67 drivers to guarantee that every data transfer has the same data valid window 4 8 3 3 Bubbles on the Bcache Data Bus...

Page 138: ...ansfer For example a ratio of 2 5 means the peak Bcache bandwidth is 16 bytes for every 2 5 GCLK cycles rd_wr The minimum spacing required between the read and write indices at the data tag pins expressed as GCLK cycles wr_rd The minimum spacing required between the write and read indices at the data tag pins expressed as GCLK cycles Term Description ...

Page 139: ...e BC_RD_WR_BUBBLES and rd_wr Use the following formula to calculate the value for the Cbox CSR BC_RD_WR_BUBBLES that produces the minimum rd_wr restriction BC_RD_WR_BUBBLES rd_wr 6 Note that a value for BC_RD_WR_BUBBLES of zero really means 64 GCLK cycles In that case amend the formula For example it is impossible to have rd_wr 6 in the 1 5x dual data rate mode case 4 8 4 Pin Descriptions This sec...

Page 140: ...using the two CSRs Table 4 44 lists the combination of control pin assertion for RAM_TYPE A Table 4 45 lists the combination of control pin assertion for RAM_TYPE B Table 4 43 Programming the Bcache Control Pins BC_PENTIUM_MODE BC_BURST_MODE_ENABLE RAM_TYPE 0 0 RAM_TYPE A 0 1 RAM_TYPE B 1 0 Unsupported 1 1 Unsupported Table 4 44 Control Pin Assertion for RAM_TYPE A TYPE_A NOP RA0 RA1 RA2 RA3 NOP N...

Page 141: ...and BcTagInClk_H pins are used to capture tag data and data from the Bcache data and tag RAMs respectively Dual data rate SSRAMs provide a clock output with the data output pins to minimize skew between the data and clock thus allowing maximum bandwidth The 21264 EV67 internally synchronizes the data to its GCLK with clock forward receive circuitry similar to that in the system interface For nonDD...

Page 142: ... is inserted between consecutive read transactions to the same bank or between consecutive write transactions 4 8 6 Disabling the Bcache for Debugging The Bcache is a required component for a 21264 EV67 based system However for debug purposes the 21264 EV67 can be operated with the Bcache disabled The Bcache can be disabled by clearing all of the BC_ENABLE bits in the Cbox WRITE_MANY CSR When disa...

Page 143: ...he Extent in the IPR For example in Figure 5 14 the field VA 47 13 resides in IPR IVA_FORM 37 3 under the stated conditions The register contents after initialization are listed in Section 7 8 Table 5 1 lists the 21264 EV67 internal processor registers Table 5 1 Internal Processor Registers Register Name Mnemonic Index Binary Score Board Bit Access MT MF Issued from Ebox Pipe Latency for MFPR Cycl...

Page 144: ... context register PCTX 01xx xxxx 4 R 0L 3 Performance counter control PCTR_CTL 0001 0100 4 RW 0L 3 Mbox IPRs DTB tag array write 0 DTB_TAG0 0010 0000 2 6 WO 0L DTB tag array write 1 DTB_TAG1 1010 0000 1 5 WO 1L DTB PTE array write 0 DTB_PTE0 0010 0001 0 4 WO 0L DTB PTE array write 1 DTB_PTE1 1010 0001 3 7 WO 0L DTB alternate processor mode DTB_ALTMODE 0010 0110 6 WO 1L DTB invalidate all process A...

Page 145: ...The RPCC instruction returns the full 64 bit value of the register Figure 5 1 shows the cycle counter register Figure 5 1 Cycle Counter Register 5 1 2 Cycle Counter Control Register CC_CTL The cycle counter control register CC_CTL is a write only register through which the lower half of the CC register may be written and its associated counter enabled and dis abled Figure 5 2 shows the cycle count...

Page 146: ...in which the faulting virtual address stored in the VA register is formatted when it is read by way of the VA_FORM register It also contains control bits that affect the behavior of the memory pipe virtual address sign extension checkers and the behavior of the Ebox extract insert and mask instructions Figure 5 4 shows the virtual address control register Figure 5 4 Virtual Address Control Registe...

Page 147: ...See the VA_FORM register section for details Reserved 29 3 VA_FORM_32 2 WO 0 This bit is used to control address formatting when reading the VA_FORM register See the section on the VA_FORM register for details VA_48 1 WO 0 This bit controls the format applied to effective virtual addresses by the VA_FORM register and the memory pipe virtual address sign extension checkers When VA_48 is clear the 4...

Page 148: ...B_TAG and ITB_PTE registers are written into the ITB entry The specific ITB entry that is written is determined by a round robin algorithm the algorithm writes to entry number 0 as the first entry after the 21264 EV67 is reset Figure 5 8 shows the ITB tag array write register Figure 5 8 ITB Tag Array Write Register 5 2 2 ITB PTE Array Write Register ITB_PTE The ITB PTE array write register ITB_PTE...

Page 149: ... 5 ITB Invalidate Single Register ITB_IS The ITB invalidate single register ITB_IS is a write only register Writing a virtual page number to this register invalidates any ITB entry that meets one of the following criteria The ITB entry s virtual page number matches ITB_IS 47 13 or fewer bits if gran ularity hint bits are set in the ITB entry and its ASN field matches the address space number suppl...

Page 150: ...t is updated by hardware when it encounters an exception or interrupt EXC_ADDR 0 is set if the associated exception occurred in PALmode The exception actions are listed here If the exception was a fault or a synchronous trap EXC_ADDR contains the PC of the instruction that triggered the fault or trap If the exception was an interrupt EXC_ADDR contains the PC of the next instruc tion that would hav...

Page 151: ...8 equals 0 and I_CTL VA_FORM_32 equals 1 Figure 5 15 Instruction Virtual Address Format Register VA_48 0 VA_FORM_32 1 5 2 9 Interrupt Enable and Current Processor Mode Register IER_CM The interrupt enable and current processor mode register IER_CM contains the inter rupt enable and current processor mode bit fields These bit fields can be written either individually or together with a single HW_MT...

Page 152: ...igure 5 17 shows the software interrupt request register Table 5 5 IER_CM Register Fields Description Name Extent Type Description Reserved 63 39 EIEN 5 0 38 33 RW External Interrupt Enable SLEN 32 RW Serial Line Interrupt Enable CREN 31 RW Corrected Read Error Interrupt Enable PCEN 1 0 30 29 RW Performance Counter Interrupt Enables SIEN 15 1 28 14 RW Software Interrupt Enables ASTEN 13 RW AST Int...

Page 153: ...ISUM read returns zeros That condition is normally assumed to be a passive release condition The interrupt is signaled again when the PALcode returns to native mode The effects of this condition can be minimized by reading ISUM twice and ORing the results Usage of ISUM in performance monitoring is described in Section 6 10 Figure 5 18 shows the interrupt summary register Figure 5 18 Interrupt Summ...

Page 154: ...32 RO Serial Line Interrupt CR 31 RO Corrected Read Error Interrupts PC 1 0 30 29 RO Performance Counter Interrupts PC0 when PC 0 is set PC1 when PC 1 is set SI 15 1 28 14 RO Software Interrupts Reserved 13 11 ASTU ASTS 10 9 RO AST Interrupts For each processor mode the bit is set if an associated AST interrupt is pending This includes the mode s ASTER and ASTRR bits and whether the processor mode...

Page 155: ...e Additionally the REG field con tains the register number of the destination specifier for the instruction that trig gered the trap Istream ACV The BAD_IVA bit of this register indicates whether the offending Istream virtual address is latched into the EXC_ADDR register or the VA register Dstream exceptions The REG field contains the register number of either the source specifier for stores or th...

Page 156: ...SET_DZE 43 RO PALcode should set FPCR DZE SET_INV 42 RO PALcode should set FPCR INV PC_OVFL 41 RO Indicates that EXC_ADDR was improperly sign extended for 48 bit mode over underflow IACV Reserved 40 14 RO 0 Reserved for Compaq BAD_IVA 13 RO Bad Istream VA This bit should be used by the IACV PALcode routine to deter mine whether the offending I stream virtual address is latched in the EXC_ADDR regi...

Page 157: ...rate instruction or the Ra field of a load or store instruction The value is UNPREDICTABLE if the trap was triggered by an ITB miss interrupt OPCDEC or other non load st operate INT 7 RO Set to indicate Ebox integer overflow trap clear to indicate Fbox trap condition IOV 6 RO Indicates Fbox convert to integer overflow or Ebox integer over flow trap INE 5 RO Indicates floating point inexact error t...

Page 158: ... 2 5 ID is 0001112 BIST_FAIL 23 RO 0 Indicates the status of BiST clear pass set fail described in Section 11 5 1 TB_MB_EN 22 RW 0 When set the hardware ensures that the virtual mode loads in DTB and ITB fill flows that access the page table and the subsequent virtual mode load or store that is being retried are ordered relative to another processor s stores This must be set for multiprocessor sys...

Page 159: ...ar 43 bit virtual address format is used and when VA_48 is set 48 bit virtual address format is used The effect of this bit on the IVA_FORM register is identical to the effect of VA_CTL VA_48 on the VA_FORM register See Section 5 1 5 When VA_48 is set the sign extension checkers generate an ACV if va 63 0 SEXT va 47 0 When VA_48 is clear the sign extension checkers generate an ACV if va 63 0 SEXT ...

Page 160: ... are used as PALshadow registers SDE 0 does not affect 21264 EV67 operation SPE 2 0 5 3 RW 0 Super Page Mode Enable Identical to the SPE bits in the Mbox M_CTL SPE 2 0 See Section 5 3 9 IC_EN 1 0 2 1 RW 3 Icache Set Enable At least one set must be enabled The entire cache may be enabled by setting both bits Zero one or two Icache sets can be enabled This bit does not clear the Icache but only disa...

Page 161: ... Icache parity or Dcache ECC errors and machine check traps can occur on any instruction in the pipeline TRP 39 RO ProfileMe Trap This bit indicates that the profiled instruction caused a trap The trap type field PMPC register and instruction at the PMPC location are needed to distinguish all trap types LS0 38 RO ProfileMe Load Store Order Trap If the profiled instruction caused a replay trap this...

Page 162: ...rupt will normally be delivered when exiting the trap PALcode flow and the EXC_ADDR register will contain the original PC that encoun tered the redirect trap PMPC 14 0 Trap 0581 ITB miss 0481 Istream Access Violation 0681 Interrupt ICM 33 RO ProfileMe Icache Miss This bit indicates that the profiled instruction was contained in an aligned 4 instruction Icache fetch block that requested a new Icach...

Page 163: ...sleep mode register SLEEP is a pseudo register that when written results in the PLL speed being reduced and the chip entering a low power mode This register must only be written after a sequence of code has been run which saves all necessary state to DRAM flushes the caches and unmasks certain interrupts so the chip can be woken up See Section 7 3 for details 5 2 21 Process Context Register PCTX T...

Page 164: ... particular AST interrupt its corresponding bits in ASTRR and ASTER must be set along with the ASTE bit in IER Further the value of the current mode bits in the PS register must be equal to or higher than the value of the mode associ ated with the AST request The bit order with this field is User Mode 12 Supervisor Mode 11 Executive Mode 10 Kernel Mode 9 ASTER 3 0 8 5 RW AST enable register used t...

Page 165: ...loating point enable if clear floating point instructions generate FEN exceptions This bit is set by hardware on reset PPCE 1 RW Process performance counting enable Enables performance counting for an individual process with counters PCTR0 or PCTR1 which are enabled by set ting PCT0_EN or PCT1_EN respectively Performance counting for the entire system can be enabled by setting I_CTL SPCE See Secti...

Page 166: ...C0 is set and an interrupt is triggered See Table 5 16 for counter modes PM_STALLED 27 RO The profiled instruction stalled for at least one cycle between the fetch and map stages of the pipeline PM_KILLED_BM 26 RO The profiled instruction was killed during or before the cycle in which it was mapped PCTR1 19 0 25 6 RW Performance counter 1 PCTR1 is enabled by I_CTL PCT1_EN and either I_CTL SPCE or ...

Page 167: ...ndicates a nontrapping profiled instruction retired valid When clear indicates that a nontrapping profiled instruction was killed after the cycle in which it was mapped Valid retire abort status for a trapping profiled instruction is determined by the trap type see I_STAT TRAP_TYPE TAK 0 RO ProfileMe conditional branch taken Indicates program branch direction if the profiled instruction is a condi...

Page 168: ...DTB_PTE arrays being written Figure 5 27 shows the DTB PTE array write registers 0 and 1 Figure 5 27 DTB PTE Array Write Registers 0 and 1 5 3 3 DTB Alternate Processor Mode Register DTB_ALTMODE The DTB alternate processor mode register DTB_ALTMODE is a write only register whose contents specify the alternate processor mode used by some HW_LD and HW_ST instructions Figure 5 28 shows the DTB altern...

Page 169: ...gisters 0 and 1 DTB_IS0 1 The Dstream translation buffer invalidate single registers DTB_IS0 and DTB_IS1 are write only pseudo registers through which software may invalidate a single entry in the DTB arrays Writing a virtual page number to one of these registers invalidates any DTB entry in the corresponding memory pipeline which meets one of the following cri teria The DTB entry s virtual page n...

Page 170: ... a LD_VPTE gets a DTB miss instruction Figure 5 31 shows the memory management status register Figure 5 31 Memory Management Status Register Table 5 18 describes the memory management status register fields Table 5 18 Memory Management Status Register Fields Description Name Extent Type Description Reserved 63 11 DC_TAG_PERR 10 RO This bit is set when a Dcache tag parity error occurred during the ...

Page 171: ... Figure 5 32 shows the Mbox control register Figure 5 32 Mbox Control Register FOR 2 RO This bit is set when a fault on read error occurs during a read transaction and PTE FOR was set ACV 1 RO This bit is set when an access violation occurs during a transac tion Access violations include a bad virtual address WR 0 RO This bit is set when an error occurs during a write transaction Table 5 18 Memory...

Page 172: ... enables superpage mapping when VA 47 41 7E16 In this mode VA 40 13 are mapped directly to PA 40 13 and PA 43 41 are copies of PA 40 sign extension SPE 0 when set enables superpage mapping when VA 47 30 3FFFE16 In this mode VA 29 13 are mapped directly to PA 29 13 and PA 43 30 are cleared Reserved 0 Bits Meaning When Set 00 Allow full time speculation 01 Force full time conservative mode Make retr...

Page 173: ... that is loaded by a fill or store Writing data that is different from that already in the block will cause bad ECC to be present Since the old ECC value will remain the ECC will be bad F_BAD_TPAR 4 WO 0 Force Bad Tag Parity When set this bit causes bad tag parity to be put into the Dcache tag array during Dcache fill operations Reserved 3 F_HIT 2 WO 0 Force Hit When set this bit causes all memory...

Page 174: ...nstructions to the Cbox shift register Each write transaction to the Cbox shift register destructively shifts six bits of information out of the Cbox error register Table 5 21 Dcache Status Register Fields Description Name Extent Type Description Reserved 63 5 SEO 4 W1C Second error occurred When set this bit indicates that a second Dcache store ECC error occurred within 6 cycles of the previous D...

Page 175: ... identical to the values written to the original CSRs Table 5 22 Cbox Data Register Fields Description Name Extent Type Description Reserved 63 6 C_DATA 5 0 5 0 RW Cbox data register A HW_MTPR instruction to this register causes six bits of data to be placed into a serial shift register When the HW_MTPR instruction is retired the data is shifted into the Cbox After the Cbox shift register has been...

Page 176: ...count BC_CLEAN_VICTIM 0 Enable clean victims to the system interface SYS_BUS_SIZE 1 0 Size of SysAddOut and SysAddOut buses SYS_BUS_FORMAT 0 Indicates system bus format SYS_CLK_RATIO 4 1 Speed of system bus Code Multiplier 0001 1 5X 0010 2 0X 0100 2 5X 1000 3 0X DUP_TAG_ENABLE 0 Enable duplicate tag mode in the 21264 EV67 PRB_TAG_ONLY 0 Enable probe tag only mode in the 21264 EV67 FAST_MODE_DISABL...

Page 177: ...tions to the pins BC_LATE_WRITE_NUM 0 2 Number of Bcache clocks to delay the data for Bcache write com mands BC_CPU_LATE_WRITE_NUM 0 1 Number of GCLK cycles to delay the Bcache clock data from index BC_BURST_MODE_ENABLE 0 Burst mode enable signal BC_PENTIUM_MODE 0 Enable Pentium mode RAM behavior SKEWED_FILL_MODE Duplicate CSR BC_FRM_CLK 0 Force all Bcache transactions to start on rising edges of ...

Page 178: ... 1 Delay of 0 to 2 phases between the forwarded clock out and address data SYS_DDMR_ENABLE 0 Enables the rising edge of the system forwarded clock always enabled SYS_DDMF_ENABLE 0 Enables the falling edge of the system forwarded clock always enabled BC_DDM_FALL_EN 0 Enables update of data address on the rising edge of the system for warded clock BC_DDM_RISE_EN 0 Enables the update of data address ...

Page 179: ...S_DDM_RISE_EN Duplicate CSR SYS_CLKFWD_ENABLE Duplicate CSR SYS_RCV_MUX_CNT_PRESET 0 1 Duplicate CSR SYS_CLK_DELAY 1 0 Duplicate CSR SYS_DDMR_ENABLE Duplicate CSR SYS_DDMF_ENABLE Duplicate CSR BC_DDM_FALL_EN Duplicate CSR BC_DDM_RISE_EN Duplicate CSR BC_CLKFWD_ENABLE Duplicate CSR BC_RCV_MUX_CNT_PRESET 1 0 Duplicate CSR SYS_CLK_DELAY 0 1 Duplicate CSR SYS_DDMR_ENABLE Duplicate CSR SYS_DDMF_ENABLE ...

Page 180: ...f Bcache clock cycles to delay signal SysDataInValid before sample by the Cbox BC_DDM_FALL_EN Duplicate CSR BC_DDM_RISE_EN Duplicate CSR BC_CPU_CLK_DELAY 0 1 Delay of Bcache clock for 0 1 2 3 GCLK cycles BC_FDBK_EN 0 7 CSR to program the Bcache forwarded clock shift register feedback points BC_CLK_LD_VECTOR 0 15 CSR to program the Bcache forwarded clock shift register load val ues BC_BPHASE_LD_VEC...

Page 181: ...2 BC_SIZE 0 3 Duplicate CSR Table 4 42 BC_ENABLE1 1 MBZ during initialization mode see Section 7 6 for information Duplicate CSR Table 4 42 BC_ENABLE1 Duplicate CSR Table 4 42 BC_ENABLE1 Duplicate CSR Table 4 42 INVAL_TO_DIRTY_ENABLE 1 WH64 acknowledges Table 4 15 ENABLE_EVICT Enable issue evict Table 4 1 BC_ENABLE Duplicate CSR Table 4 42 INVAL_TO_DIRTY_ENABLE 0 WH64 acknowledges Table 4 15 BC_EN...

Page 182: ...N_CACHE_BLOCK x47FF041F align with nops mb wait for MEM OP s to complete lda r0 x0086 r31 load I_CTL hw_mtpr r0 EV6__I_CTL SDE 2 IC_EN 3 SBE 0 br r0 create dest address addq r0 17 r0 finish computing dest address hw_mtpr r31 EV6__IC_FLUSH flush the Icache bne r31 separate retires hw_jmp_stall r0 force flush ALIGN_CACHE_BLOCK x47FF041F align with nops bc_config mb pull this block in Icache lda r1 x...

Page 183: ...EM_ERR or xxx_BC_ERR then C_STS contains the status of the block as follows otherwise the value of C_STS is X C_ADDR 6 42 Address of last reported ECC or parity error If C_STAT value is DSTREAM_DC_ERR only bits 6 19 are valid If C_STAT value is DOUBLE_BIT_ERROR and SKEWED_FILL_MODE 0 is set then C_ADDR is X Bits Error Status 0 0 0 0 0 Either no error or error on a speculative load or a Bcache vic ...

Page 184: ......

Page 185: ...ing system spe cific programming interface that is common across all Alpha microprocessors The actual implementation of PALcode differs for each operating system PALcode runs with privileges enabled instruction stream Istream mapping disabled and interrupts disabled PALcode has privilege to use five special opcodes that allow functions such as physical data stream Dstream references and internal p...

Page 186: ... In each of these cases PALcode routines are used to provide the function The routines are nothing more than programs invoked at specified times and read in as Istream code in the same way that all other Alpha code is read Once invoked however PALcode runs in a special mode called PALmode 6 2 PALmode Environment PALcode runs in a special environment called PALmode defined as follows Istream memory...

Page 187: ...architecture for implementation spe cific use These opcodes are privileged and are only available in PALmode These instructions generally produce an OPCDEC exception if executed while the pro cessor is not in PALmode If I_CTL HWE is set these instructions can also be exe cuted in kernel mode Software that uses these instructions must adhere to the PALcode restrictions listed in this section 6 4 1 ...

Page 188: ...e address for the HW_LD instruction is physical It is the load lock version of the HW_LD instruction 0102 Virtual VPTE Flags a virtual PTE fetch LD_VPTE Used by trap logic to distinguish a single TB miss from a double TB miss Kernel mode access checks are performed 1002 Virtual The effective address for the HW_LD instruction is virtual 1012 Virtual WrChk The effective address for the HW_LD instruc...

Page 189: ...hed a PC onto the stack the HINT field should be set to 00 to keep the stack from being modified In the rare circumstance that the HW_RET instruction might be used like a JSR or JSR_COROUTINE the stack can be managed by setting the HINT bits accordingly See Section D 25 for more information about the HW_RET instruction Figure 6 3 shows the HW_RET instruction format Table 6 4 HW_ST Instruction Fiel...

Page 190: ...rget PC of the HW_RET instruction Bit 0 of the register s contents determines the new value of PALmode 15 14 HINT 00 01 10 11 HW_JMP The PC is not pushed onto the prediction stack The predicted target is PC 4 DISP 12 0 HW_JSR The PC is pushed onto the prediction stack The predicted target is PC 4 DISP 12 0 HW_RET The prediction is popped off the stack and used as the target HW_COROUTINE The predic...

Page 191: ...at explicitly read the value of the IPR Implicit readers are instructions whose behavior is affected by the value of the IPR For example each load instruction is an implicit reader of the DTB Explicit writers are HW_MTPR instructions that explicitly write a value into the IPR Implicit writers are instructions that may write a value into the IPR as a side effect of execution For example a load inst...

Page 192: ...ny of scoreboard bits 3 0 are set when a load or store instruction enters the IQ that load or store instruction will not be issued from the IQ until those scoreboard bits are clear Scoreboard bits 3 0 are cleared when the HW_MTPR instructions that set them are issued or are aborted Bits 7 4 are cleared when the HW_MTPR instructions that set them are retired or are aborted Bits 3 0 are used for the...

Page 193: ...ll of the paired instruction orderings between instructions of the four IPR access types It specifies whether access order must be maintained and if so the mechanisms used to ensure correct ordering Table 6 7 Paired Instruction Fetch Order Second Instruction First Instruction Implicit Reader Implicit Writer Explicit Reader Explicit Writer Implicit Reader Read transac tions can be reordered No IPRs...

Page 194: ...the score board mechanism is not sufficient For example modification of the ITB affects instructions before the issue state of the pipeline In this case PALcode must contain a HW_RET instruction with its stall bit set before any instruction that implicitly reads the IPR s in question This prevents instructions that are newer than the HW_RET instruction from being successfully fetched issued and re...

Page 195: ...isters called shadow registers which are available to PALcode for use as scratch space and storage for commonly used values These registers are made available under the control of the SDE 1 field of the I_CTL IPR These shadow registers overlay R4 through R7 and R20 through R23 when the CPU is in PALmode and SDE 1 is set PALcode generally runs with shadow mode enabled Any PALcode that supports CALL...

Page 196: ...ap to the MT_FPCR PALcode entry point The PALcode can return using a HW_RET instruction with its STALL bit set This sequence ensures that the MT_FPCR instruc tion will be correctly ordered for subsequent readers of the FPCR 6 8 PALcode Entry Points PALcode is invoked at specific entry points of which there are two classes CALL_PAL and exceptions 6 8 1 CALL_PAL Entry Points CALL_PAL entry points ar...

Page 197: ... point at a PC determined by the type of exception The return PC of the instruction that triggered the exception is placed in the EXC_ADDR register and onto the return predic tion stack Table 6 8 shows the PALcode exception entry locations and their offset from the PAL_BASE IPR Table 6 8 PALcode Exception Entry Locations Entry Name Type Offset16 Description DTBM_DOUBLE_3 Fault 100 Dstream TB miss ...

Page 198: ...t original va bicp7 1 p7 clear double miss flag xorp4 p6 p4 interlock p4 and p6 xorp4 p6 p4 restore p4 trap__dtbm_single_vpte hw_ldq v p4 p4 1L get vpte bltp_misc trap__d1to1 xU 63 1 1 to 1 blbcp4 trap__invalid_dpte xU invalid branch andp4 x80 p7 isolate mb bit xorp7 x80 p7 flip mb bit ALIGN_FETCH_BLOCK x47FF041F PVC_VIOLATE 2 ignore scoreboard violation hw_mtprp6 EV6__DTB_TAG0 2 6 0L write tag0 h...

Page 199: ...able IPR scoreboard bits 3 0 are used to order the restarted load or store instructions for the DTB write transactions MM_STAT and VA will not be overwritten if the LD_VPTE instruction misses the DTB There is no issue order constraint The code is written to prevent a later execution of the DTB fill instruction from being issued before a previous execution and corrupting the previous write to the T...

Page 200: ... of the DTB are ordered relative to the creation of a new DTB entry whether all sub sequent loads and stores to the loaded address will hit in the DTB If DTB_PTEx GH is zero the scoreboard mechanism alone is sufficient If DTB_PTEx GH is not zero the scoreboard mechanism alone is not suffi cient although this is not a problem In this case the new DTB entry is not visible to subsequent load store in...

Page 201: ...native code is running 1 to 1 that is running in a mode where the physical address should be mapped 1 to 1 to the virtual address rather than being taken from a page table The HW_RET instruction should have its STALL bit set to ensure that the restarted Istream does not read the ITB until the ITB is written As an alternative to using I_CTL TB_MB_EN 1 to enforce read ordering I_CTL TB_MB_EN can be ...

Page 202: ...if that counter is disabled To avoid that interrupt the PALcode should clear the interrupt by writing to HW_INT_CLR Interrupts are disabled in PALmode As a quirk of the implementation while counting is disabled a read of PCTR_CTL can yield value some increment where value is the actual value in PCTR_CTL and incre ment for PCTR0 is in the range 0 4 retired instructions in that cycle and increment f...

Page 203: ...le 6 10 to note which counter overflowed in the handler s data structures The handler may read the counter to see how many events have happened since the overflow The handler may also choose to write the counters to control the frequency of inter rupts IPR Name Relevant Fields Meaning IER_CM PCEN 1 0 Enable Interrupts PCTX PPCE Enable Process Performance Counting or use I_CTL SPCE PCTR_CTL SL0 Sel...

Page 204: ... This input counts the number of times the Bcache result was a miss Essentially a long latency probe is a data request from other processes that cause Bcache misses in a system This count is phase shifted three cycles early and thus includes events that occurred three cycles before the start and before the end of the ProfileMe window 6 10 2 3 4 Mbox replay traps cycles This input counts Mbox repla...

Page 205: ...ned in I_STAT overcount 2 0 3 Count If PCTR0 and PCTR1 are enabled they increment according to modes selected by SL0 SL1 4 End window The last cycle of the window depends on whether the instruction traps retires aborts and or is squashed by the fetcher Table 6 12 CMOV Decomposed Instruction New Instructions CMOV Ra Rb Rc CMOV1 Ra oldRc newRc1 CMOV2 newRc1 Rb newRc2 IPR Name Relevant Fields Meaning...

Page 206: ...ed from counting until PCTR_CTL is next written 5 Interrupt PALcode When ISUM field PC 1 0 is set execution of PCTR0 s or PCTR1 s interrupt PAL code is performed 6 Operating system interrupt handler The handler should first read the IPRs in Table 6 13 and then write PCTR_CTL to set up the next interrupt Table 6 13 ProfileMe Mode Returned IPR Contents IPR Name Relevant Fields Meaning PMPC 63 0 All ...

Page 207: ...rder The inum retire delay of Y is cycle in which Y retired cycle in which X retired A large inum retire delay indicates a possible performance bottleneck for example an instruction stalled on a data cache miss 6 10 3 3 3 Retired instructions cycles When counting retired instructions in ProfileMe mode the final count in PCTR0 may include instructions that retired before the ProfileMe window and ma...

Page 208: ...ProfileMe Mode Table 6 14 shows the counter modes that are used with ProfileMe mode Table 6 14 ProfileMe Mode PCTR_CTL Input Select Fields SL0 4 SL1 3 2 PCTR0 PCTR1 1 00 Retired instructions Cycle counting 1 01 Cycle counting Inum retire delay 1 10 Retired instructions Bcache miss or long latency probes 1 11 Cycle counting Mbox replay traps ...

Page 209: ...rations 7 1 Power Up Reset Flow and the Reset_L and DCOK_H Pins The 21264 EV67 reset sequence is triggered using the two input signals Reset_L and DCOK_H in a sequence that is described in Section 7 1 1 After Reset_L is deasserted the following sequence of operations takes place Table 7 1 21264 EV67 Reset State Machine Major Operations Operation Function Ramp up Sequence the PLL input and output d...

Page 210: ...nsfer of control should be to addresses not loaded in the Icache by the SROM interface or the Icache may provide unexpected instructions 5 Typically any state required by the PALcode is initialized and then the console is started switching out of PALmode and into native mode The console code initial izes and configures the system and boots an operating system from an I O device such as a disk or t...

Page 211: ...OE_L Tristated BcDataInClk_H 7 0 NA input BcTagOutClk_x Tristated BcDataOE_L Tristated BcTagParity_H Tristated BcDataOutClk_x 3 0 Tristated BcTagShared_H Tristated BcDataWr_L Tristated BcTagValid_H Tristated BcLoad_L Tristated BcTagWr_L Tristated BcTag_H 42 20 Tristated BcVref NA I_DC_REF BcTagDirty_H Tristated System Interface IRQ_H 5 0 NA input SysDataInClk_H 7 0 NA input SysAddIn_L 14 0 NA inpu...

Page 212: ...cluding the value of the PLL Ydiv divisor which specifies the ratio of the system clock to the internal clock see Section 7 11 2 3 and enables the charge pump on the phase locked loop SysAddOut_L 14 0 Initially during power up reset state is not defined If not during power up preserves previous state Then after the clock forward reset period as the external clocks start signal driven to NZNOP unti...

Page 213: ... Time Function Value PllBypass_H Continuous input Select ClkIn_x onto GCLK instead of internal PLL 0 Bypass1 1 Use PLL ClkFwdRst_H Sampling method according to IRQ_H 4 Reset_L Continuous input IRQ_H 5 Rising edge of DCOK_H Select 1 1 FrameClk mode Internal FrameClk can be generated two ways 0 Sample with FrameClk_H 1 Use a copy of EV6Clk_H IRQ_H 4 Rising edge of DCOK_H Select method of sampling Cl...

Page 214: ...l about 20 µs The state machine then goes into the RAMP2 state changing the effective input frequency to ClkIn 1 for an additional lock interval about 20 µs The lock periods are generated by the internal duration counter which is driven by GCLK The counter counts 4108 GCLK cycles during the ClkIn_x 2 lock interval Note that GCLK is produced by the output of the PLL which is locking to an input clo...

Page 215: ...scription Constraint ClkIn_x Differential clocks that are inputs to PLL or are bypassed onto GCLK directly Clocks must be running before DCOK_H is asserted PLL_VDD VDD supply to PLL PLL_VDD must lead VDD VDD VDD supply to the 21264 EV67 chip logic except PLL DCOK_H Logic signal to the 21264 EV67 that the VDD supply is good Reset_L RESET pin asserted by SYSTEM to the 21264 EV67 Reset_L must be asse...

Page 216: ...erform ing any BiST One deassert to initialize the clock forwarding interface The 21264 EV67 then begins fetching code at PAL_BASE 0x780 Figure 7 2 shows the fault reset sequence of operation In Figure 7 2 note the follow ing symbols for constraints and information Constraints Information Table 7 5 Effect on IPRs After Fault Reset IPR After Reset PAL_BASE Maintained not reset I_CTL Bit value 3 bot...

Page 217: ...lushing the caches The sleep mode sequence of operations is triggered by the PALcode twice performing a HW_MTPR to the Ibox SLEEP IPR The first write prevents the assertion of ClkFwdRst_H from fault resetting the chip The PALcode then informs the system in an implementation dependent way that it may assert ClkFwdRst_H On the second HW_MTPR to the SLEEP IPR the PLL begins to ramp down and the 21264...

Page 218: ...nternal arrayed structures The SROM is not reloaded Instead the 21264 EV67 begins fetching code from the system at address PAL_BASE 0x780 Figure 7 3 shows the sleep mode sequence of operations In Figure 7 3 note the fol lowing constraint and informational symbols Constraints Informational symbols Table 7 6 Effect on IPRs After Transition Through Sleep Mode IPR Effects After Transition Through Slee...

Page 219: ...t_H Signal asserted by the system to initialize and reset clock forwarding interfaces ClkFwdRst_H must be asserted by the system when entering sleep mode The system deasserts ClkFwdRst_H no sooner than one FrameClk_H cycle after sourcing an interrupt to the 21264 EV67 Forwarded clocks Bit clocks forwarded to from the 21264 EV67 Clocks stop running under ClkFwdRst_H System interrupt Asynchronous in...

Page 220: ...story table The external second level cache Bcache is disabled by Reset_L The Bcache must be initialized by PALcode before it is enabled 7 6 Initialization Mode Processing The initialization mode allows the 21264 EV67 to generate and manipulate cache blocks before the system interface has been initialized Within the 21264 EV67 the Cbox configuration registers are divided into the WRITE_ONCE and th...

Page 221: ...al Figure 7 4 shows a code example for initializing Bcache Figure 7 4 Example for Initializing Bcache Reset chip and load Icache with this code set init_mode now all WrVictims are ignored bc_enable_a 1 zeroblk_enable_a 1 set_dirty_enable_a 0 init_mode_a 1 enable_evict_a 0 bc_wrt_sts_a 0 bc_bank_enable_a 0 bc_size_a 15 now all writes to Bcache actually invalidate the Bcache if space was needed for ...

Page 222: ...nfiguration dictated by the reset state of the IPR bits that select the configuration options The response to system interface commands and internally generated memory accesses is determined by this default configuration System environments that are not compati ble with the default configuration must use the SROM Icache load feature to initially load and execute a PALcode program to configure the ...

Page 223: ...C_FLUSH Icache flush X CLR_MAP Clear virtual to physical map X SLEEP Sleep mode X PCTX Ibox process context PCTX FPE is set All other bits are cleared PCTR_CTL Performance counter control X Must be cleared in PALcode Ebox IPRs CC Cycle counter X Must be cleared in PALcode CC_CTL Cycle counter control X Must be cleared in PALcode VA Virtual address X VA_FORM Virtual address format X VA_CTL Virtual ...

Page 224: ...d approximate state transition equations Note that there are implicit transitions from each state to an appropriate down ramp state when Reset_L is asserted DTB_IS0 DTB invalidate single array 0 X DTB_IS1 DTB invalidate single array 1 X DTB_ASN0 DTB address space number 0 Cleared DTB_ASN1 DTB address space number 1 Cleared MM_STAT Memory management status X M_CTL Mbox control Cleared DC_CTL Dcache...

Page 225: ...K frequency An internal duration counter is initial ized to count 4108 GCLK cycles WAIT_ SETTLE 16 32 WAIT_ NOMINAL 16 32 RAMP1 2 4 RAMP2 1 2 WAIT_ClkFwd Rst0 WAIT_ClkFwd Rst1 RUN FAULT_ RESET DOWN3 16 32 DOWN2 2 4 DOWN1 1 2 COLD WAIT_ BiSI WAIT_ BiST BiSI finished Counter finished Reset_L deasserted Reset_L asserted DCOK_H asserted Counter finished ClkFwdRst_H deasserted Counter finished No BiST ...

Page 226: ...n must be synchronous to a rising edge of FrameClk_H 21264 EV67 uses this synchronous event to reset the clock forwarding interface and deassert internal reset 21264 EV67 subsequently begins running code either preloaded in the SROM or located in memory and begins system transactions RUN Chip is running software interface is reset and system transactions can be processed From power up the Icache s...

Page 227: ... test point to measure the PLL phase alignment They do not provide a clock source EV6Clk_x are square wave signals that drive rail to rail continually from 0 to 2 1 volts 7 11 2 3 Nominal Operating Frequency Under normal operating conditions the frequency of the PLL output clock GCLK is a simple function of the Ydiv divider value DOWN2 Triggered by duration counter reaching 8205 cycles the PLL ram...

Page 228: ...the PLL to generate a global clock that is distributed throughout the 21264 EV67 with a frequency range of 1 MHz to 500 MHz The presence of the global clock during this period avoids permanent damage to the 21264 EV67 GCLK Reference Clock Frequency MHz for Ydiv Dividers1 1 Dividers 11 through 16 are out of range for the 21264 EV67 and reserved for future use Valid refer ence clock ClkIn_x frequenc...

Page 229: ...ry system port data correctable ECC error Bcache data correctable ECC error on a probe Double bit fill errors Error case summary Table 8 1 summarizes the 21264 EV67 error detection Table 8 1 21264 EV67 Error Detection Mechanisms Component Error Detection Mechanism Bcache tag Parity protected Bcache data array Quadword ECC protected Dcache tag array Parity protected Dcache duplicate tag array Parit...

Page 230: ...d instructions do not come directly from the Icache 2 I_STAT PAR is set 3 A corrected read data CRD interrupt is posted when enabled Pass 3 only 8 3 Dcache Tag Parity Error The primary copies of the Dcache tags are used only when servicing 21264 EV67 gener ated load and store instructions There are correctable and uncorrectable forms of this error If an issued load or store instruction detects a D...

Page 231: ...her in the same cycle as the Dcache tag probe typical case or in some subsequent cycle load queue retry The hardware functional flows for these two error cases differ slightly When a load instruction reads the Dcache data array in the same cycle as the tag array if an ECC error occurs on the LSD ECC error detectors then the Ibox stops retiring instructions and does not resume retiring until after ...

Page 232: ...t A corrected read data CRD error interrupt is posted when enabled 8 4 3 Dcache Victim Extracts Dcache victims with an ECC error are scrubbed as they are written into the victim data buffer No status is logged No exception is posted 8 5 Dcache Store Second Error A second store instruction error is logged when it occurs close behind the first Neither error is corrected DC_STAT ECC_ERR_ST is set DC_...

Page 233: ...ctim during an ECB instruction or during a Dcache Bcache miss The recovery mechanism depends on the action that triggered the error 8 8 1 Icache Fill from Bcache For an Icache fill the LSD ECC checkers detect the error and bad Icache data parity is generated for the octaword that contains the quadword in error If an error is detected the following actions are taken The hardware flushes the Icache ...

Page 234: ...stage of the pipeline until the error is corrected With a READ_ERR read type from the Mbox for the load instruction in error the Cbox scrubs the block in the Dcache by evicting the block into the victim buffer and writing it back into the Dcache C_STAT DSTREAM_BC_ERR is set C_ADDR contains bits 42 6 of the Bcache fill address of the block that contains the error C_SYNDROME_0 7 0 and C_SYNDROME_1 7...

Page 235: ...e Icache C_STAT ISTREAM_MEM_ERR is set C_ADDR contains bits 42 6 of the system memory fill address of the block that contains the error C_SYNDROME_0 7 0 and C_SYNDROME_1 7 0 contain the syndrome of quadword 0 and 1 respectively of the octaword subblock that contains the error A machine check MCHK is posted and taken immediately The PALcode machine check handler performs a scrubbing operation as de...

Page 236: ...and 1 respectively of the octaword subblock that contains the error The load queue retries the load instruction and rewrites the register DC_STAT ECC_ERR_LD is set A corrected read data CRD error interrupt is posted when enabled Note Errors in speculative load instructions cause a CRD error to be posted but the data is not scrubbed by hardware The PALcode cannot scrub the data because C_STAT is ze...

Page 237: ...e MCHK is taken when not in PALmode A double bit fill error from memory marked by the data s corresponding ECC when written to cache also writes the corresponding ECC to cache Any consumer of that error such as another CPU also consumes the corresponding ECC value Note C_ADDR may be inaccurate in heavy traffic conditions C_STAT is accu rate 8 12 Error Case Summary Table 8 3 summarizes the various ...

Page 238: ... CRD DC_STAT ECC_ERR_LD C_STAT DSTREAM_BC_ERR C_ADDR error address C_SYNDROME_0 C_SYNDROME_1 Corrected and scrubbed in Dcache3 Scrub error as described in Section D 36 Log as CRD Bcache victim read on Dcache Bcache miss CRD DC_STAT ECC_ERR_LD C_STAT contains 0 None Log as CRD Bcache victim read on ECB None None None None Memory single bit error on Icache fill MCHK and CRD2 C_STAT ISTREAM_MEM_ERR C...

Page 239: ...n Dcache fill MCHK1 C_STAT DSTREAM_MEM_DBL C_ADDR error address 4 None Log as MCHK 1 Machine check taken in native mode It is deferred while in PALmode 2 CRD error posted in case the machine check is down a speculative path 3 For a single bit error on a non target quadword the error is not corrected in hardware but is corrected by PALcode during the scrub operation 4 The contents of C_ADDR may not...

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Page 241: ... under the given maximum electrical ratings may cause permanent device failure Functionality at or above these limits is not implied Exposure to these limits for extended periods of time may affect device reliability Power data is preliminary and based on measurements from a limited set of material Table 9 1 Maximum Electrical Ratings Characteristics Ratings Storage temperature 55 C to 125 C 67 F ...

Page 242: ...e The test load must be 1M ohm In nor mal operation these inputs are coupled with a 680 pF capacitor 3 Functional operation of the 21264 EV67 with less than all VDD and VSS pins con nected is not implied 4 The test load is a 50 ohm resistor to VDD 2 The resistor can be connected to the 21264 EV67 pin by a 50 ohm transmission line of any length 5 DC test conditions set the minimum swing required Th...

Page 243: ...e 9 4 Input DC Reference Pin I_DC_REF Parameter Symbol Description Test Conditions Minimum Maximum VREF DC input reference voltage 600 mV VDD 650 mV II Input current VSS V VDD 150 µA Table 9 5 Input Differential Amplifier Receiver I_DA Parameter Symbol Description Test Conditions Minimum Maximum VIL Low level input voltage Note 5 VREF 200 mV VIH High level input voltage VREF 200 mV II Input curren...

Page 244: ...t VSS V VDD 150 µA1 CIN Input pin capacitance Freq 10 MHz 5 7 pF Note 6 1 Measurement taken with output driver disabled Table 9 9 Pin Type Open Drain Driver for Test Pins O_OD_TP Parameter Symbol Description Test Conditions Minimum Maximum VOL Low level output voltage IOL 15 mA 400 mV IOZ High impedance output current 0 V VDD 150 µA COD_TP Pin capacitance Freq 10 MHz 5 2 pF Note 6 Table 9 10 Bidir...

Page 245: ...ent conditions which can compromise the reliability of the receiving chip 3 Finally no CMOS chip should see an input voltage that is higher than its internal VDD In such a condition a reasonable level of charge can be injected into the bulk of the die This condition can expose the chip to a positive feedback latchup condition The 21264 EV67 addresses those three failure mechanisms by disabling all...

Page 246: ...ailure mechanism number three systems must sequence input and bidirectional pins I_DA I_DA_CLK B_DA_OD B_DA_PP and I_DC_REF such that the 21264 EV67 does not see a voltage above its VDD In addition as power is being ramped Reset_L must be asserted this allows the 21264 EV67 to reset internal state Once the target voltage levels are attained systems should assert DCOK_H This indicates to the 21264 ...

Page 247: ...InClk_L 400 ps 400 ps NA NA 1 0 V ns SysDataOutValid_L I_DA SysAddInClk_L 400 ps 400 ps NA NA 1 0 V ns SysAddInClk_L I_DA NA NA NA NA 45 55 1 0 V ns SysAddOut_L 14 0 O_OD SysAddOutClk_L NA NA 300 ps3 NA NA SysAddOutClk_L O_OD EV6Clk_x NA NA 400 ps 45 55 NA SysData_L 63 0 B_DA_OD SysDataInClk_H 7 0 400 ps 400 ps NA NA 1 0 V ns SysDataOutClk_L 7 0 4 NA NA 300 ps3 NA NA SysCheck_L 7 0 B_DA_OD SysData...

Page 248: ...romClk_H 2 0 ns 2 0 ns NA 100 mV ns SromOE_L O_OD EV6Clk_x NA NA 2 0 ns SromClk_H20 O_OD EV6Clk_x NA NA 7 0 ns Tms_H I_DA Tck_H 2 0 ns 2 0 ns NA NA 100 mV ns Trst_L21 I_DA Tck_H NA NA NA NA 100 mV ns Tdi_H I_DA Tck_H 2 0 ns 2 0 ns NA NA 100 mV ns Tdo_H O_OD Tck_H NA NA 7 0 ns NA NA Tck_H I_DA IEEE 1149 1 Port Freq 5 0 MHz Max NA NA NA 45 55 100 mV ns TestStat_H O_OD EV6Clk_x NA NA 4 0 ns NA NA 1 T...

Page 249: ...kIn_x is running This pin must either be deasserted during power up or the 21264 EV67 core power pin VDD pins indicating the 21264 EV67 s internal PLL will be used Note that it is illegal to use PllBypass_H asserted during power up unless a ClkIn_x is present 15 See Section 7 11 2 for a discussion of ClkIn_x as it relates to operating the 21264 EV67 s internal PLL versus running the 21264 EV67 in ...

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Page 251: ...ied to operate when the temperature at the center of the heat sink Tc is as shown in Table 10 1 Temperature Tc should be measured at the center of the heat sink between the two package studs The GRAFOIL pad is the interface mate rial between the package and the heat sink Note Compaq recommends using the heat sink because it greatly improves the ambient temperature requirement Table 10 1 Operating ...

Page 252: ...ype 31 C 1 Heat sink type 3 has a 80 mm 80 mm 15 mm fan attached 55 1 Table 10 4 Maximum Ta for 21264 EV67 667 MHz and 2 0 V with Various Airflows Airflow linear ft min 100 200 400 800 1000 Maximum Ta with heat sink type 1 C 30 7 48 9 51 1 Maximum Ta with heat sink type 2 C 21 2 45 3 54 0 55 5 Maximum Ta with heat sink type 31 C 1 Heat sink type 3 has a 80 mm 80 mm 15 mm fan attached 50 4 Table 10...

Page 253: ...rious Airflows Airflow linear ft min 100 200 400 800 1000 Maximum Ta with heat sink type 1 C 22 1 42 6 45 1 Maximum Ta with heat sink type 2 C 38 5 48 4 50 0 Maximum Ta with heat sink type 31 C 44 3 1 Heat sink type 3 has a 80 mm 80 mm 15 mm fan attached Table 10 8 Maximum Ta for 21264 EV67 833 MHz and 2 0 V with Various Airflows Airflow linear ft min 100 200 400 800 1000 Maximum Ta with heat sink...

Page 254: ...10 4 Thermal Management Alpha 21264 EV67 Hardware Reference Manual Heat Sink Specifications Figure 10 1 Type 1 Heat Sink 25 4 mm 1 0 in 32 5 mm 1 280 in 80 5 mm 3 17 in 80 5 mm 3 17 in FM 06119 AI4 ...

Page 255: ...e Manual Thermal Management 10 5 Heat Sink Specifications Figure 10 2 shows the heat sink type 2 along with its approximate dimensions Figure 10 2 Type 2 Heat Sink 25 4 mm 1 0 in 44 5 mm 1 75 81 0 mm 3 19 in 81 0 mm 3 19 in FM 06120 AI4 ...

Page 256: ...imate dimensions The cooling fins of heat sink type 3 are cross cut Also an 80 mm 80 mm 15 mm fan is attached to heat sink type 3 Figure 10 3 Type 3 Heat Sink 80 0 mm 3 15 in Fan Fan 15 mm 0 59 in 1 62 in 80 0 mm 3 15 in 71 5 mm 2 815 in 80 0 mm 3 15 in 71 5 mm 2 815 in 25 4 mm 1 0 in 70 65 mm 2 815 in 40 0 mm 1 575 in 27 3 mm 1 075 in FM 06121 AI4 ...

Page 257: ...PCB with the heat sink fins aligned with the airflow direction Avoid preheating ambient air Place the 21264 EV67 on the PCB so that inlet air is not preheated by any other PCB components Do not place other high power devices in the vicinity of the 21264 EV67 Do not restrict the airflow across the 21264 EV67 heat sink Placement of other devices must allow for maximum system airflow in order to maxi...

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Page 259: ... port IEEE 1149 1 port TestStat_H pin Power up self test and initialization Notes on IEEE 1149 1 operation and compliance The 21264 EV67 has several manufacturing test features that are used only by the fac tory and they are beyond the scope of this chapter 11 1 Test Pins The 21264 EV67 test access ports include the IEEE 1149 1 test access port a dual pur pose SROM Serial diagnostic terminal port ...

Page 260: ...TROM flag is set the rate is 16 times the CPU clock rate The hold time on SromData_H is 2 CPU cycle time with respect to SromClk_H The SromData_H pin reads data from the SROM Every data and tag bit in Icache is loaded by that sequence 11 2 2 Serial Terminal Port After the SROM data is loaded into the Icache the three SROM interface signals can be used as a software UART and the pins become paralle...

Page 261: ...Bypass Register The Bypass Register provides a short shift path through the chip s IEEE 1149 1 logic It is generally useful at the board level testing It consists of a 1 bit shift register The Instruction Register holds test instructions On the 21264 EV67 this register is 5 bits wide Table 11 2 describes the supported instructions The instruction set supports several public and private instruction...

Page 262: ...ther wise it is asserted high and remains high until chip is reset again Figure 11 2 pictori ally shows the behavior of the pin during the power up operations Note A system designer may sample the TestStat_H pin on the first rising edge of the SromClk_H pin to determine BiST results After the power up dur ing the normal chip operation whenever the 21264 EV67 does not retire an instruction for 2K C...

Page 263: ...00 CPU cycles The result of self test is made available as Pass Fail status on the TestStat_H pin see Section 11 4 The result of self test is also available in an IPR bit Software can read this status through IPR I_CTL 23 0 pass 1 fail See Section 5 2 15 The power up BiST leaves all bits in all arrays initialized to zeroes The instruction cache and the tag are reinitialized as part of the SROM ini...

Page 264: ...istory bits are loaded serially from offchip serial ROMs Once the serial load has been invoked by the chip reset sequence the cache is loaded from the lower to the higher addresses The serial Icache fill invoked by the chip reset sequence operates internally at a fre quency of Table 11 3 lists the Icache bit fields in an SROM line Fetch bits are listed in the order of shift direction to down and t...

Page 265: ... implemented on the board 2 Tms_H should not change when Trst_L is being deasserted References IEEE Std 1149 1 1993 A Test Access Port and Boundary Scan Architecture See Appendix B for a listing of the Boundary Scan Register Table 11 3 Icache Bit Fields in an SROM Line Fetch Bit Icache Data Fetch Bit Icache Data Fetch Bit Icache Data 0 par MBZ 86 par MBZ 172 lp_train 1 c 3 87 c 0 173 175 lp_src 2 ...

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Page 267: ...g point conformance A 1 Alpha Instruction Summary This section contains a summary of all Alpha architecture instructions All values are in hexadecimal radix Table A 1 describes the contents of the Format and Opcode col umns that are in Table A 2 Table A 1 Instruction Format and Opcode Notation Instruction Format Format Symbol Opcode Notation Meaning Branch Bra oo oo is the 6 bit opcode field Float...

Page 268: ...ic Format Opcode Description ADDF F P 15 080 Add F_floating ADDG F P 15 0A0 Add G_floating ADDL Opr 10 00 Add longword ADDL V Opr 10 40 Add longword with integer overflow enable ADDQ Opr 10 20 Add quadword ADDQ V Opr 10 60 Add quadword with integer overflow enable ADDS F P 16 080 Add S_floating ADDT F P 16 0A0 Add T_floating AMASK Opr 11 61 Architecture mask AND Opr 11 00 Logical product BEQ Bra 3...

Page 269: ...CMPLE Opr 10 6D Compare signed quadword less than or equal CMPLT Opr 10 4D Compare signed quadword less than CMPTEQ F P 16 0A5 Compare T_floating equal CMPTLE F P 16 0A7 Compare T_floating less than or equal CMPTLT F P 16 0A6 Compare T_floating less than CMPTUN F P 16 0A4 Compare T_floating unordered CMPULE Opr 10 3D Compare unsigned quadword less than or equal CMPULT Opr 10 1D Compare unsigned qu...

Page 270: ... F P 15 0A3 Divide G_floating DIVS F P 16 083 Divide S_floating DIVT F P 16 0A3 Divide T_floating ECB Mfc 18 E800 Evict cache block EQV Opr 11 48 Logical equivalence EXCB Mfc 18 0400 Exception barrier EXTBL Opr 12 06 Extract byte low EXTLH Opr 12 6A Extract longword high EXTLL Opr 12 26 Extract longword low EXTQH Opr 12 7A Extract quadword high EXTQL Opr 12 36 Extract quadword low EXTWH Opr 12 5A ...

Page 271: ...rt quadword high INSQL Opr 12 3B Insert quadword low INSWH Opr 12 57 Insert word high INSWL Opr 12 1B Insert word low ITOFF F P 14 014 Integer to floating move F_floating ITOFS F P 14 004 Integer to floating move S_floating ITOFT F P 14 024 Integer to floating move T_floating JMP Mbr 1A 0 Jump JSR Mbr 1A 1 Jump to subroutine JSR_COROUTINE Mbr 1A 3 Jump to subroutine return LDA Mem 08 Load address ...

Page 272: ...rd minimum MSKBL Opr 12 02 Mask byte low MSKLH Opr 12 62 Mask longword high MSKLL Opr 12 22 Mask longword low MSKQH Opr 12 72 Mask quadword high MSKQL Opr 12 32 Mask quadword low MSKWH Opr 12 52 Mask word high MSKWL Opr 12 12 Mask word low MT_FPCR F P 17 024 Move to FPCR MULF F P 15 082 Multiply F_floating MULG F P 15 0A2 Multiply G_floating MULL Opr 13 00 Multiply longword MULL V Opr 13 40 Multip...

Page 273: ...ord by 8 S8SUBQ Opr 10 3B Scaled subtract quadword by 8 SEXTB Opr 1C 00 Sign extend byte SEXTW Opr 1C 01 Sign extend word SLL Opr 12 39 Shift left logical SQRTF F P 14 08A Square root F_floating SQRTG F P 14 0AA Square root G_floating SQRTS F P 14 08B Square root S_floating SQRTT F P 14 0AB Square root T_floating SRA Opr 12 3C Shift right arithmetic SRL Opr 12 34 Shift right logical STB Mem 0E Sto...

Page 274: ...BQ Opr 10 29 Subtract quadword SUBQ V Opr 10 69 Subtract quadword with integer overflow enable SUBS F P 16 081 Subtract S_floating SUBT F P 16 0A1 Subtract T_floating TRAPB Mfc 18 0000 Trap barrier UMULH Opr 13 30 Unsigned multiply quadword high UNPKBL Opr 1C 35 Unpack bytes to longwords UNPKBW Opr 1C 34 Unpack bytes to words WH64 Mfc 18 F800 Write hint 64 bytes WMB Mfc 18 4400 Write memory barrie...

Page 275: ...am load instructions HW_ST 1F PAL1F Performs Dstream store instructions HW_REI 1E PAL1E Returns instruction flow to the program counter PC pointed to by EXC_ADDR internal processor register IPR HW_MFPR 19 PAL19 Accesses the Ibox Mbox and Dcache IPRs HW_MTPR 1D PAL1D Accesses the Ibox Mbox and Dcache IPRs Table A 5 IEEE Floating Point Instruction Function Codes Mnemonic None C M D U UC UM UD ADDS 0...

Page 276: ... 7BC 73C 77C 7FC CVTQT 7BE 73E 77E 7FE CVTTS 5AC 52C 56C 5EC 7AC 72C 76C 7EC DIVS 583 503 543 5C3 783 703 743 7C3 DIVT 5A3 523 563 5E3 7A3 723 763 7E3 MULS 582 502 542 5C2 782 702 742 7C2 MULT 5A2 522 562 5E2 7A2 722 762 7E2 SQRTS 58B 50B 54B 5CB 78B 70B 74B 7CB SQRTT 5AB 52B 56B 5EB 7AB 72B 76B 7EB SUBS 581 501 541 5C1 781 701 741 7C1 SUBT 5A1 521 561 5E1 7A1 721 761 7E1 Mnemonic None S CVTST 2AC...

Page 277: ...e of the 11 bit function code field for the floating point instructions that are not directly tied to IEEE or VAX floating point The opcode for the following instructions is 1716 Table A 6 VAX Floating Point Instruction Function Codes Mnemonic None C U UC S SC SU SUC ADDF 080 000 180 100 480 400 580 500 ADDG 0A0 020 1A0 120 4A0 420 5A0 520 CMPGEQ 0A5 4A5 CMPGLE 0A7 4A7 CMPGLT 0A6 4A6 CVTDG 09E 01E...

Page 278: ... For example the third row 2 A under the 1016 column contains the symbol INTS representing the all integer shift instructions The opcode for those instructions would then be 1216 because the 0 in 10 is replaced by the 2 in the Offset column Likewise the third row under the 1816 column contains the symbol JSR representing all jump instructions The opcode for those instructions is 1A because the 8 i...

Page 279: ...br BGT br Table A 9 Key to Opcode Summary Used in Table A 8 Symbol Meaning FLTI IEEE floating point instruction opcodes FLTL Floating point operate instruction opcodes FLTV VAX floating point instruction opcodes FPTI Floating point to integer register move opcodes INTA Integer arithmetic instruction opcodes INTL Integer logical instruction opcodes INTM Integer multiply instruction opcodes INTS Int...

Page 280: ...ngs for Signaling NaN and Quiet NaN are defined by the Alpha Architecture Handbook Version 4 The 21264 EV67 accepts infinity operands and implements infinity arithmetic as defined by the IEEE standard and the Alpha Architecture Handbook Version 4 The 21264 EV67 implements SQRT for single SQRTS and double SQRTT pre cision in hardware Note In addition the 21264 EV67 also implements the VAX SQRTF and...

Page 281: ...leared If an exception is detected and the corresponding trap is enabled by the instruction and is not disabled by the FPCR control bits the 21264 EV67 will record the condition in the EXC_SUM register and initiate an arithmetic trap The following items apply to Table A 11 The 21264 EV67 traps on a denormal input operand for all arithmetic operations unless FPCR DNZ 1 Input operand traps take prec...

Page 282: ...x SQRTx INPUT Inf operand Inf none QNaN operand QNaN none SNaN operand QNaN Invalid Op A A not 0 CQNaN Invalid Op 0 0 none SQRTx OUTPUT Inexact result root Inexact CMPTEQ CMPTUN INPUT Inf operand True or False none QNaN operand False for EQ True for UN none SNaN operand False for EQ True for UN Invalid Op CMPTLT CMPTLE INPUT Inf operand True or False none QNaN operand False Invalid Op SNaN operand...

Page 283: ...T Inexact result Result Inexact Integer overflow Truncated result Invalid Op CVTif OUTPUT Inexact result Result Inexact CVTff INPUT Inf operand Inf none QNaN operand QNaN none SNaN operand QNaN Invalid Op CVTff OUTPUT same as ADDx FBEQ FBNE FBLT FBLE FBGT FBGE LDS LDT STS STT CPYS CPYSN FCMOVx Table A 11 Exceptional Input and Output Conditions Continued Alpha Instructions 21264 EV67 Hardware Suppl...

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Page 285: ...ven in Section B 1 1 B 1 1 BSDL Description of the Alpha 21264 EV67 Boundary Scan Register alpha21264 EV67 bsdl The BSDL Description for EV6 s IEEE 1149 1 Circuits Revision History Rev Date Description 1 0 Feb 99 First external release entity Alpha_21264 EV67 is ref B 8 generic PHYSICAL_PIN_MAP string PGA_EV6 ref B 8 2 port ref B 8 3 TestStat_H out bit SromOE_L out bit SromClk_H out bit SromData_H...

Page 286: ...in bit_vector 0 to 14 SysAddInClk_L in bit SysAddOutClk_L out bit JWB added SysVref linkage bit JWB added SysFillValid_L in bit SysDataInValid_L in bit SysDataOutValid_L in bit Spare_0 linkage bit n c MiscVref linkage bit Spare_2 linkage bit n c Tdi_H in bit Tdo_H out bit Trst_L in bit Tck_H in bit Tms_H in bit VSS linkage bit_vector 0 to 103 VDD linkage bit_vector 0 to 93 use STD_1149_1_1994 all ...

Page 287: ...C9 B6 B4 D4 G5 D2 H4 G1 N5 L1 N1 U3 W5 W1 AB2 AC3 AD4 AF4 AJ3 AK4 AN1 AM4 AU5 BA1 BA3 BC3 BD6 BA9 BC9 AY12 A39 D36 A41 B42 D42 D44 H40 H42 G45 L43 L45 N45 T44 U45 W45 AA43 AC43 AD44 AE41 AG45 AK44 AL43 AM42 AR45 AP40 BA45 AV42 BB44 BB42 BC41 BA37 BD40 BcCheck_H F2 AB4 AT2 BC11 M38 AB42 AU43 BC37 M8 AA3 AW1 BD10 E45 AC45 AT44 BB36 BcDataInClk_H E7 R3 AH2 BC5 F38 U39 AH44 AY40 Spare_7 F8 T4 AJ1 BD4 ...

Page 288: ...38 M42 AM44 Y2 AY4 B8 H14 BD20 D28 F36 D40 V42 AV44 AF2 D6 P8 AV14 F22 BB28 AY36 K40 AH42 BD44 AM2 K6 Y8 BD14 AY22 F30 B38 T40 AP42 AV2 T6 AF8 F16 A23 AY30 H38 AB40 AY42 AB6 BD8 AY16 F24 B32 P38 AD40 B44 F4 AD6 F10 D18 AY24 H32 Y38 AK40 H44 M4 AK6 AY10 BB18 B26 AV32 AF38 AT40 P44 constant numeric_EV6 PIN_MAP_STRING SysAddIn_L 559 536 468 580 445 490 558 579 467 534 511 421 556 577 443 SysAddInClk_...

Page 289: ...heck_H 112 283 394 527 206 288 408 540 205 275 432 549 111 297 401 517 BcDataInClk_H 92 227 330 524 130 246 337 474 Spare_7 115 235 338 546 108 254 344 496 BcDataOutClk_L 187 411 192 400 BcDataOutClk_H 180 403 184 392 BcTag_H 95 163 5 27 73 96 6 142 51 164 74 29 52 8 98 30 9 121 76 99 54 77 166 BcTagValid_H 33 BcTagDirty_H 55 BcTagShared_H 145 BcTagParity_H 32 BcTagOE_L 167 BcTagWr_L 101 BcTagInCl...

Page 290: ...Voltage CLKIN_H CLKIN_L attribute TAP_SCAN_CLOCK of Tck_H signal is 5 0e6 LOW attribute TAP_SCAN_IN of Tdi_H signal is TRUE attribute TAP_SCAN_OUT of Tdo_H signal is TRUE attribute TAP_SCAN_MODE of Tms_H signal is TRUE attribute TAP_SCAN_RESET of Trst_L signal is TRUE attribute COMPLIANCE_PATTERNS of Alpha_21264 EV67 entity is Ref B 8 10 See Note 4 DcOk_H 1 attribute INSTRUCTION_LENGTH of Alpha_21...

Page 291: ... BC_2 BcData_H 27 BIDIR x 339 0 Z 333 BC_2 BcData_H 91 BIDIR x 339 0 Z 332 BC_2 SysData_L 27 BIDIR x 336 0 WEAK1 331 BC_2 BcData_H 26 BIDIR x 339 0 Z 330 BC_2 BcData_H 90 BIDIR x 339 0 Z 329 BC_2 SysData_L 26 BIDIR x 336 0 WEAK1 328 BC_2 BcData_H 25 BIDIR x 339 0 Z 327 BC_2 BcData_H 89 BIDIR x 339 0 Z 326 BC_2 SysData_L 25 BIDIR x 336 0 WEAK1 325 BC_2 BcData_H 24 BIDIR x 339 0 Z 324 BC_2 BcData_H ...

Page 292: ...NPUT x 271 BC_2 SysDataOutClk_L 1 OUTPUT2 x 270 BC_3 CONTROL 0 sccell2 269 BC_3 SysDataInClk_H 1 INPUT x 268 BC_2 BcData_H 11 BIDIR x 273 0 Z 267 BC_2 BcData_H 75 BIDIR x 273 0 Z 266 BC_2 SysData_L 11 BIDIR x 270 0 WEAK1 265 BC_2 BcData_H 10 BIDIR x 273 0 Z 264 BC_2 BcData_H 74 BIDIR x 273 0 Z 263 BC_2 SysData_L 10 BIDIR x 270 0 WEAK1 262 BC_2 BcData_H 9 BIDIR x 273 0 Z 261 BC_2 BcData_H 73 BIDIR ...

Page 293: ...208 0 Z 208 BC_3 CONTROL 0 tccell0 207 BC_3 BcTagInClk_H INPUT x 206 BC_2 BcTag_H 34 BIDIR x 208 0 Z 205 BC_2 BcTag_H 35 BIDIR x 208 0 Z 204 BC_2 BcTag_H 36 BIDIR x 208 0 Z 203 BC_2 BcTag_H 37 BIDIR x 208 0 Z 202 BC_2 BcTag_H 38 BIDIR x 208 0 Z 201 BC_2 BcTag_H 39 BIDIR x 208 0 Z 200 BC_2 BcTag_H 40 BIDIR x 208 0 Z 199 BC_2 BcTag_H 41 BIDIR x 208 0 Z 198 BC_2 BcTag_H 42 BIDIR x 208 0 Z 197 BC_2 Bc...

Page 294: ...0 Z 140 BC_2 SysData_L 39 BIDIR x 150 0 WEAK1 139 BC_2 BcData_H 103 BIDIR x 153 0 Z 138 BC_2 BcData_H 39 BIDIR x 153 0 Z 137 BC_2 SysCheck_L 4 BIDIR x 150 0 WEAK1 136 BC_2 BcCheck_H 12 BIDIR x 153 0 Z 135 BC_2 BcCheck_H 4 BIDIR x 153 0 Z 134 BC_2 BcDataOutClk_H 2 OUTPUT2 x 133 BC_2 BcDataOutClk_L 2 OUTPUT2 x 132 BC_2 SysData_L 40 BIDIR x 119 0 WEAK1 131 BC_2 BcData_H 104 BIDIR x 116 0 Z 130 BC_2 B...

Page 295: ...2 BcData_H 118 BIDIR x 84 0 Z 75 BC_2 BcData_H 54 BIDIR x 84 0 Z 74 BC_2 SysData_L 55 BIDIR x 87 0 WEAK1 73 BC_2 BcData_H 119 BIDIR x 84 0 Z 72 BC_2 BcData_H 55 BIDIR x 84 0 Z 71 BC_2 SysCheck_L 6 BIDIR x 87 0 WEAK1 70 BC_2 BcCheck_H 14 BIDIR x 84 0 Z 69 BC_2 BcCheck_H 6 BIDIR x 84 0 Z 68 BC_2 BcDataOutClk_H 3 OUTPUT2 x 67 BC_2 BcDataOutClk_L 3 OUTPUT2 x 66 BC_2 SysData_L 56 BIDIR x 53 0 WEAK1 65 ...

Page 296: ...PUT x 17 BC_3 SysAddIn_L 1 INPUT x 16 BC_3 SysAddIn_L 2 INPUT x 15 BC_3 SysAddIn_L 3 INPUT x 14 BC_3 SysAddIn_L 4 INPUT x 13 BC_3 SysAddIn_L 5 INPUT x 12 BC_3 SysAddIn_L 6 INPUT x 11 BC_3 SysAddIn_L 7 INPUT x 10 BC_3 SysAddIn_L 8 INPUT x 9 BC_3 SysAddInClk_L INPUT x 8 BC_3 SysAddIn_L 9 INPUT x 7 BC_3 SysAddIn_L 10 INPUT x 6 BC_3 SysAddIn_L 11 INPUT x 5 BC_3 SysAddIn_L 12 INPUT x 4 BC_3 SysAddIn_L ...

Page 297: ...Alpha 21264 EV67 Hardware Reference Manual Serial Icache Load Predecode Values C 1 C Serial Icache Load Predecode Values See the Alpha Motherboards Software Developer s Kit SDK for information ...

Page 298: ......

Page 299: ...etch blocks must contain four valid instructions each and must not contain any retire logic NOP instructions reset 1 Initialize 80 retirator done status bits and the integer and floating mapper destinations 2 Do A MTPR ITB_IA which turns on the mapper source enables 3 Create a map stall to complete the ITB_IA State after execution of this code retirator initialized destinations mapped source mappi...

Page 300: ...13 initialize Int Reg 13 addt f31 f31 f12 initialize F P Reg 12 mult f31 f31 f13 initialize F P Reg 13 addq r31 r31 r14 initialize Int Reg 14 addq r31 r31 r15 initialize Int Reg 15 addt f31 f31 f14 initialize F P Reg 14 mult f31 f31 f15 initialize F P Reg 15 addq r31 r31 r16 initialize Int Reg 16 addq r31 r31 r17 initialize Int Reg 17 addt f31 f31 f16 initialize F P Reg 16 mult f31 f31 f17 initial...

Page 301: ...ddq r31 r31 r0 initialize retirator 73 addq r31 r31 r0 initialize retirator 74 addq r31 r31 r0 initialize retirator 75 addq r31 r31 r0 initialize retirator 76 addq r31 r31 r0 initialize retirator 77 addq r31 r31 r0 initialize retirator 78 addq r31 r31 r0 initialize retirator 79 addq r31 r31 r0 initialize retirator 80 stop deleting mtpr r31 EV6__ITB_IA flush the ITB SCRBRD 4 this also turns on mapp...

Page 302: ... in next block tch0 br r31 tch1 fetch in next block nxt1 mtpr r31 EV6__IER_CM clear IER_CM SCRBRD 4 creates a map stall under the above mtpr to SCRBRD 4 addq r31 r31 r0 nop br r31 nxt2 continue executing in next block tch1 br r31 tch2 fetch in next block nxt2 addq r31 r31 r0 1st buffer fetch block for above map stall addq r31 r31 r0 nop br r31 nxt3 continue executing in next block tch2 br r31 tch3...

Page 303: ...block and because sbe 0 and because we do an mb at the beginning which blocks further progress until the entire block has been fetched in we don t have to fool with pulling this code in before executing it undef bc_enable_a undef init_mode_a undef bc_size_a undef zeroblk_enable_a undef enable_evict_a undef set_dirty_enable_a undef bc_bank_enable_a undef bc_wrt_sts_a define bc_enable_a 0 define ini...

Page 304: ...D 1 5 mtpr r0 EV6__DTB_PTE0 write DTB_PTE0 SCRBRD 0 4 mtpr r0 EV6__DTB_PTE1 write DTB_PTE1 SCRBRD 3 7 mtpr r31 EV6__SIRR clear SIRR SCRBRD 4 lda r0 0x08FF r31 load FPCR sll r0 52 r0 initial FPCR value itoft r0 f0 nop itoftr0 f0 value 0x8FF0000000000000 mt_fpcr f0 nop mt_fpcrf0 f0 f0 do the load lda r0 0x2086 r31 load I_CTL ldah r0 0x0050 r0 TB_MB_EN 1 CALL_PAL_R23 1 SL_XMIT 1 SBE 0 SDE 2 IC_EN 3 m...

Page 305: ... jsr_init_loop_nxt JSR to PC 4 jsr_init_loop_nxt stq_p r1 0x780 r31 flush Pipe 0 ST logic subq r0 1 r0 decrement loop count beq r0 jsr_init_done done br r31 jsr_init_loop continue loop jsr_init_done lda r0 0x03FF r31 create FP one sll r0 52 r0 value 0x3FF0000000000000 itoft r0 f0 put it into F0 reg addq r31 r31 r1 nop also clears R1 mult f0 f0 f0 flush mul pipe addt f0 f0 f0 flush add pipe divt f0...

Page 306: ...appear in the same fetch block octaword aligned octaword Multiple explicit writers to IPRs that are not in the same scoreboard group can appear If this restriction is violated the IPR readers might not see the in order state Also the IPR might ultimately end up with a bad value D 3 Restriction 4 No Writers and Readers to IPRs in Same Score board Group This restriction is made for the convenience o...

Page 307: ...normally wait before being issued This would have the undesired consequence of allowing newer load and store instructions to be issued out of order A deadlock can occur if issuing the instructions out of order causes the floating point store instruction to continually replay the trap To avoid the deadlock on a floating point store instruction replay trap the source register dirty status is not che...

Page 308: ...resses must ensure proper sign extension for the selected value of I_CTL VA_48 When I_CTL VA_48 is clear indicating 43 bit vir tual address format PALmode physical Istream addresses must sign extend address bits above bit 42 although the physical address range is 44 bits An illegal address can only be generated by a PALmode JSR type instruction or a HW_RET instruction returning to a PALmode addres...

Page 309: ...instruc tions After the delimiting instruction defined above retires these registers are unlocked and may change due to new exception conditions If a second exception occurs before the registers are unlocked it will be either delayed or forced to replay trap a non PALmode trap until the register has been unlocked After being unlocked a subsequent new path exception condition will be allowed to rel...

Page 310: ...STx FTOIx where x is any applicable FP data type but does not include LDx ITOFx D 15 Restriction 19 HW_RET STALL After Updating the FPCR by way of MT_FPCR in PALmode FPCR updating occurs in hardware based on the retirement of a nontrapping version of MT_FPCR in PALcode Use a HW_RET STALL after the nontrapping MT_FPCR to achieve minimum latency four cycles between the retiring of the MT_FPCR and th...

Page 311: ...rantees through the register dependency on R0 that neither HW_MTPR are issued before scoreboard bits 7 4 are cleared There must be a HW_RET STALL after an HW_MTPR IS0 HW_MTPR IS1 pair Also these two writes must be executed atomically that is either both must be retired or neither may be retired D 19 Restriction 23 HW_ST P CONDITIONAL Does Not Clear the Lock Flag A HW_ST P CONDITIONAL will not clea...

Page 312: ...quired in the reset PALcode to initialize the ITB It is also required that PALcode not be exited even via a mispredicted path until this HW_MTPR ITB_IA has been retired PALmode can change temporarily after fetching a HW_RET regardless of the STALL qualifier down a mispredicted path leading to use of the ITB before it is actually initialized Unexpected instruction fetch and execution can occur foll...

Page 313: ...fter the HW_MFPR MM_STAT The VA VA_FORM and DC_CTL registers require a similar constraint All LOAD instructions except HW_LD might modify any or all of these registers HW_LD does not modify MM_STAT D 25 Guideline 29 JSR JMP RET and JSR_COR in PALcode Unprivileged JSR JMP RET and JSR_COR instructions will always mispredict when used in PALcode In addition HW_RET to a PALmode target will always misp...

Page 314: ...ext block ALIGN_CACHE_BLOCK sys__cbox_over1 block 1 addq r31 11 p6 initialize shift count 11x addq r31 r31 p7 initialize shift data br r31 sys__cbox_over2 go to block 2 sys__cbox_touch1 br r31 sys__cbox_touch2 touch block 2 sys__cbox_over2 block 2 hw_mtpr r31 EV6__SHIFT_CONTROL 6 0L shift in 6 bits subq p6 1 p6 decrement shift count br r31 sys__cbox_over3 go to block 3 sys__cbox_touch2 br r31 sys_...

Page 315: ...all D 27 Restriction 31 I_CTL VA_48 Update The VA_48 virtual address format cannot be changed while executing a JSR JMP GOTO JSR_COROUTINE or HW_RET instruction A simple method of ensuring that the address does not change is to write I_CTL twice in two separate fetch blocks with the same data The second write will stall the pipeline and ensure that the mode cannot change even down a mispredicted p...

Page 316: ...Updating I_CTL SDE A software interlock is required between updates of the I_CTL SDE and a subsequent instruction fetch that may use any destination registers A suggested method of ensuring this interlock is to use two MTPR I_CTL instructions in separate fetch blocks followed by three more fetch blocks of non NOP instructions D 33 Restriction 37 Updating VA_CTL VA_48 A software interlock is requir...

Page 317: ...lls the hardware flushes the Icache but the PALcode must scrub the block in the Bcache and memory On Bcache and Memory single bit errors on Dcache fills the hardware scrubs the Dcache as long as the error was on a target quadword but the PALcode must scrub the Dcache for non target quadwords and must in general scrub the block in the Bcache and memory The scrub consists of reading each quadword in...

Page 318: ...1 ldq r6 x10 r4 re read the bad block QW 2 ldq r6 x18 r4 re read the bad block QW 3 ldq r6 x20 r4 re read the bad block QW 4 ldq r6 x28 r4 re read the bad block QW 5 ldq r6 x30 r4 re read the bad block QW 6 mb no other mem ops till done ldq_l r6 x38 r4 re read the bad block QW 7 stq_c r6 x38 r4 now store it to force scrub mb and r6 r31 r6 consumer of above beq r6 sys__crd_scrub_done these 2 lines ...

Page 319: ...s trap or hw_ret_stall D 39 Restriction 43 No Trappable Instructions Along with HW_MTPR There are two parts to this restriction 1 There cannot be any mispredictable trappable instructions together with an HW_MTPR in the current fetch block 2 There cannot be any mispredictable trappable instructions in the previous fetch block D 40 Restriction 44 Not Applicable to the 21264 EV67 D 41 Restriction 45...

Page 320: ...er nor mal circumstances the intention would be for a HW_RET to wait until the MTPR issues and that can only be enforced by putting the two instructions in different fetch blocks In this case the intention is for the HW_RET to issue before the MTPR The hardware does not enforce the scoreboarding when the two instructions are in the same fetch block and thus the HW_RET can issue and mispredict befo...

Page 321: ...2X bcache bis r31 r31 s5 Set ADDR 0x0 hw_stq p s5 104 r31 Store ADDR for next pass thru subq s5 s2 s5 mb Make sure no speculative loads happen in the CRD handler align 4 NOP_OPCODE blbc r31 4 br r31 4 V align 4 NOP_OPCODE Make sure no speculative loads happen in the CRD handler next_reread four cache blocks Evict dcache by prefetching to all dcache indexes use hw_ldl r31 xxxx Normal Prefetch Do no...

Page 322: ...ce Bad Data ECC and Force D 44 Restriction 48 MB Bracketing of Dcache Writes to Force Bad Data ECC and Force Bad Tag Parity Writes to DC_CTL F_BAD_DECC and DC_CTL DCDAT_ERR_EN must be brack eted by MB instructions to quiesce the memory system The Istream must also be qui esced before and during the sequence as described in Section D 26 ...

Page 323: ... 72 15 8 BcDataInClk_H 1 BcDataOutClk_x 0 BcCheck_H 9 1 BcDataInClk_H 1 BcDataOutClk_x 0 BcData_H 87 80 23 16 BcDataInClk_H 2 BcDataOutClk_x 1 BcCheck_H 10 2 BcDataInClk_H 2 BcDataOutClk_x 1 BcData_H 95 88 31 24 BcDataInClk_H 3 BcDataOutClk_x 1 BcCheck_H 11 3 BcDataInClk_H 3 BcDataOutClk_x 1 BcData_H 103 96 39 32 BcDataInClk_H 4 BcDataOutClk_x 2 BcCheck_H 12 4 BcDataInClk_H 4 BcDataOutClk_x 2 BcDa...

Page 324: ...264 EV67 Signal Name or Board Connection Late Write SSRAM Data Pin Name BcAdd_H 21 4 SA_H 17 0 BcDataOutClk_H 3 0 CK_H Set from board to 1 2 the 21264 EV67 core voltage CK_L BcData_H 127 0 BcCheck_H 15 0 DQx BcDataWr_L SW_L Unconnected Tck_H Unconnected Tdo_H Unconnected Tms_H Unconnected Tdi_H From board pull down to VSS G_L From board pull down to VSS SBx_L From board pull down to VSS or BcDataO...

Page 325: ... Unconnected TMS_H Unconnected TDI_H Unconnected TCK_H Unconnected TDC_H Table E 4 Dual Data Rate SSRAM Data Pin Usage 21264 EV67 Signal Name or Board Connection Dual Data Rate SSRAM Data Pin Name BcAdd_H 21 4 SA_H 17 0 BcData_H 33 20 BcCheck_H 15 0 DQx BcLoad_L LD_L B1 BcDataWr_L R W_L B2 From board pulled up to VDD LBO_L From board pulled down to VSS Q_L BcDataInClk_H CQ_H BcDataOutClk_H CK_H Bc...

Page 326: ... From board pulled up to VDD LBO_L From board pulled down to VSS Q_L SA 19 18 BcTagInClk_H CQ_H BcTagOutClk_H CK_H BcTagOutClk_L CK_L Set from board to 1 2 core voltage VREF1_H VREF2_H Set from board implementation dependent ZQ_H BcTagValid_H DQx BcTagDirty_H DQx BcTagShared_H DQx BcTagParity_H DQx Unconnected or terminated CQ_L From board pulled up to VDD TCK_H Unconnected TDO_H From board pulled...

Page 327: ...text switch occurs ASNs are processor specific the hardware makes no attempt to maintain coherency across multiple processors address translation The process of mapping addresses from one address space to another ALIGNED A datum of size 2 N is stored in memory at a byte address that is a multiple of 2 N that is one that has N low order zeros ALU Arithmetic logic unit ANSI American National Standar...

Page 328: ...memory barrier instruc tion Bcache See second level cache bidirectional Flowing in two directions The buses are bidirectional they carry both input and output signals BiSI Built in self initialization BiST Built in self test bit Binary digit The smallest unit of data in a binary notation system designated as 0 or 1 bit time The total time that a signal conveys a single valid piece of information s...

Page 329: ...undary The bits are numbered right to left 0 through 7 byte granularity Memory systems are said to have byte granularity if adjacent bytes can be written con currently and independently by different processes or processors cache See cache memory cache block The smallest unit of storage that can be allocated or manipulated in a cache Also known as a cache line cache coherence Maintaining cache cohe...

Page 330: ... copies of data recently used by the processor and fetches several bytes of data from memory in anticipation that the processor will access the next sequential series of bytes The 21264 EV67 microprocessor contains two onchip internal caches See also write through cache and write back cache cache miss The status returned when cache memory is probed with no valid cache entry at the probed address C...

Page 331: ...ol and status register CSR A device or controller register that resides in the processor s I O space The CSR ini tiates device activity and records its status CPI Cycles per instruction CPU See central processing unit CSR See control and status register cycle One clock interval data bus A group of wires that carry data Dcache Data cache A cache reserved for storage of data The Dcache does not cont...

Page 332: ...e written to memory DMA See direct memory access DRAM Dynamic random access memory Read write memory that must be refreshed read from or written to periodically to maintain the storage of information DTB Data translation buffer Also defined as Dstream translation buffer DTL Diode transistor logic dual issue Two instructions are issued in parallel during the same microprocessor cycle The instructio...

Page 333: ...h a period that is two times the bit time Forwarded clocks must be 50 duty cycle clocks whose rising and falling edges are aligned with the changing edge of the data FPGA Field programmable gate array FPLA Field programmable logic array FQ Floating point issue queue framing clock The framing clock defines the start of a transmission either from the system to the 21264 EV67 or from the 21264 EV67 t...

Page 334: ...on the 21264 EV67 used to store instructions The Icache con tains 8KB of memory space It is a direct mapped cache Icache blocks or lines con tain 32 bytes of instruction stream data with associated tag as well as a 6 bit ASM field and an 8 bit branch history field per block Icache does not contain hardware for main taining cache coherency with memory and is unaffected by the invalidate bus IDU A l...

Page 335: ...r IPGA Interstitial pin grid array IQ Integer issue queue ITB Instruction translation buffer JFET Junction field effect transistor latency The amount of time it takes the system to respond to an event LCC Leadless chip carrier LFSR Linear feedback shift register load store architecture A characteristic of a machine architecture where data items are first loaded into a pro cessor register operated ...

Page 336: ...t only updates a subset of a nominal data block MBO See must be one Mbox This section of the processor unit performs address translation interfaces to the Dcache and performs several other functions MBZ See must be zero MESI protocol A cache consistency protocol with full support for multiprocessing The MESI protocol consists of four states that define whether a block is modified M exclusive E sha...

Page 337: ...lpha those with an initial fraction bit of 0 and quiet NaNs for Alpha those with an initial fraction bit of 1 NATURALLY ALIGNED See ALIGNED NATURALLY ALIGNED data Data stored in memory such that the address of the data is evenly divisible by the size of the data in bytes For example an ALIGNED longword is stored such that the address of the longword is evenly divisible by 4 NMOS N type metal oxide...

Page 338: ...rchitecturally defined behavior PALmode A special environment for running PALcode routines parameter A variable that is given a specific value that is passed to a program before execution parity A method for checking the accuracy of data by calculating the sum of the number of ones in a piece of binary data Even parity requires the correct sum to be an even num ber odd parity requires the correct ...

Page 339: ...ine and a negative voltage pull up resistor A resistor placed between a signal line to a positive voltage QNaN Quiet Nan See NaN quad issue Four instructions are issued in parallel during the same microprocessor cycle The instructions use different resources and so do not conflict quadword Eight contiguous bytes starting on an arbitrary byte boundary The bits are numbered from right to left 0 thro...

Page 340: ...il to perform its intended functions during a specified time interval when operated under stated conditions reset An action that causes a logic unit to interrupt the task it is performing and go to its ini tialized state RISC Reduced instruction set computing A computer with an instruction set that is paired down and reduced in complexity so that most can be performed in a single processor cycle H...

Page 341: ... location and fully asso ciative organization in which data from anywhere in main memory can be put any where in the cache An n way set associative cache allows data from a given address in main memory to be cached in any of n locations SIMM Single inline memory module SIP Single inline package SIPP Single inline pin package SMD Surface mount device SNaN Signaling NaN See Nan SRAM See SSRAM SROM S...

Page 342: ...mory operation is a hit or a miss on that cache block target clock Skew controlled clock that receives the output of the RECEIVE MUX TB Translation buffer tristate Refers to a bused line that has three states high low and high impedance TTL Transistor transistor logic UART Universal asynchronous receiver transmitter UNALIGNED A datum of size 2 N stored at a byte address that is not a multiple of 2...

Page 343: ... Used in reference to a cache block in the cache of a system bus node The cache block is valid but is about to be replaced due to a cache block resource conflict victim address file The victim address file and the victim data file together form an 8 entry buffer used to hold information for transactions to the Bcache and main memory victim data file The victim address file and the victim data file...

Page 344: ...ations may use the copies and write operations use additional state to determine whether there are other copies to invalidate or update WRITE_BLOCK A transaction where the 21264 EV67 requests that an external logic unit process write data write data wrapping System feature that reduces apparent memory latency by allowing write data cycles to differ the usual low to high sequence Requires cooperati...

Page 345: ...E Cbox CSR 4 47 defined 5 36 BC_CLOCK_OUT Cbox CSR 4 45 BC_CPU_CLK_DELAY Cbox CSR 4 44 4 45 defined 5 38 BC_CPU_LATE_WRITE_NUM Cbox CSR defined 5 35 BC_DDM_FALL_EN Cbox CSR 4 47 defined 5 36 BC_DDM_RISE_EN Cbox CSR 4 47 defined 5 36 BC_DDMF_ENABLE Cbox CSR 4 47 defined 5 35 BC_DDMR_ENABLE Cbox CSR 4 47 defined 5 35 BC_ENABLE Cbox CSR 4 51 5 39 7 12 BC_FDBK_EN Cbox CSR 4 46 defined 5 38 BC_FRM_CLK ...

Page 346: ...k_x signal pins 3 4 4 43 BcDataWr_L signal pin 3 4 4 44 BcLoad_L signal pin 3 4 4 44 BcTag_H signal pins 3 4 4 44 BcTagDirty_H signal pin 3 4 4 44 BcTagInClk_H signal pin 3 4 4 44 using 4 53 BcTagOE_L signal pin 3 4 4 44 BcTagOutClk_x signal pins 3 4 4 44 BcTagParity_H signal pin 3 4 4 44 BcTagShared_H signal pin 3 4 4 44 BcTagValid_H signal pin 3 4 4 44 BcTagWr_L signal pin 3 4 4 44 BcVref signal...

Page 347: ... signal pin 3 4 4 30 with system initialization 7 7 ClkIn_x signal pins 3 4 Clock forwarding 7 4 CLR_MAP clear virtual to physical map register 5 21 at power on reset state 7 15 CMOV instruction special cases of 2 26 COLD reset machine state 7 17 Commands 21264 EV67 to system 4 19 system to 21264 EV67 4 26 when to NXM 4 38 Conventions xix abbreviations xix address xx aligned xx bit notation xx cau...

Page 348: ...e 7 15 DTB_ASN0 address space number register 0 at power on reset state 7 16 DTB_ASN0 address space number registers 0 5 28 DTB_ASN1 address space number register 1 5 28 at power on reset state 7 16 DTB_IA invalidate all process register 5 27 at power on reset state 7 15 DTB_IAP invalidate all ASM 0 process register 5 27 at power on reset state 7 15 DTB_IS0 invalidate single array 0 register 5 27 ...

Page 349: ...defined 5 34 Fault reset flow 7 8 Fault reset sequence of operations 7 9 FAULT_RESET reset machine state 7 18 Fbox described 2 10 executed in pipeline 2 16 FEN fault 6 13 FetchBlk 21264 EV67 command 4 22 4 39 system probes with 4 41 FetchBlkSpec 21264 EV67 command 4 22 4 39 Field notation convention xxi Floating point arithmetic trap pipeline abort delay with 2 16 Floating point control register 2...

Page 350: ... PMPC 5 8 register rename maps 2 6 retire logic 2 8 retire logic and mapper required sequence for D 1 sleep mode register SLEEP 5 21 software interrupt request register SIRR 5 10 subsections in 2 2 virtual program counter logic 2 2 IC_FLUSH Icache flush register at power on reset state 7 15 IC_FLUSH_ASM Icache flush ASM register 5 21 Icache data errors 8 2 error case summary for 8 9 fill from Bcac...

Page 351: ...lidate single register 5 7 at power on reset state 7 15 ITB_MISS fault 6 14 ITB_PTE array write register 5 6 at power on reset state 7 14 ITB_TAG array write register 5 6 at power on reset state 7 14 IVA_FORM instruction virtual address format register 5 9 at power on reset state 7 15 J JITTER_CMD Cbox CSR defined 5 38 JMP misprediction in PALcode D 15 JSR misprediction in PALcode D 15 pipeline ab...

Page 352: ...with 2 27 merging rules 2 30 store instructions with 2 29 Memory barrier instructions translation to external interface 4 5 Memory barriers 2 32 Memory reference unit See Mbox MF_FPCR instruction 6 12 Microarchitecture summarized 2 1 MiscVref signal pin 3 5 Miss address file 2 13 I O address space loads 2 28 memory address space loads 2 28 memory address space stores 2 29 MM_STAT memory management...

Page 353: ...put clocks 7 19 ramp up 7 6 PLL_IDD values for 9 3 PLL_VDD signal pin 3 5 PLL_VDD values for 9 3 PllBypass_H signal pin 3 5 PMPC ProfileMe register 5 8 Ports IEEE 1149 1 11 3 serial terminal 11 2 SROM load 11 2 Power maximum 9 1 sleep defined 9 3 Power supply sequencing 9 5 Power on flow signals and constraints 7 7 reset flow 7 1 self test and initialization 11 5 timing sequence 7 3 PRB_TAG_ONLY C...

Page 354: ... reset machine state 7 18 RW n convention xx S SAMPLE public instruction B 1 Scrubbing single bit errors D 19 I_CTL Ibox control register updating I_CTL D 18 Second level cache See Bcache Security holes with UNPREDICTABLE results xxii Serial terminal port 11 2 SET_DIRTY_ENABLE Cbox CSR 4 23 5 39 7 12 programming 4 24 SharedToDirty 21264 EV67 command 4 22 4 40 system probes with 4 41 Signal name co...

Page 355: ... 38 SYS_FRAME_LD_VECTOR Cbox CSR 4 19 4 31 defined 5 38 SYS_RCV_MUX_CNT_PRESET Cbox CSR 4 31 defined 5 36 SYS_RCV_MUX_PRESET Cbox CSR 4 33 SysAddIn_L signal pins 3 5 SysAddInClk_L signal pin 3 5 SysAddOut_L signal pins 3 5 SysAddOutClk_L signal pin 3 5 SYSBUS_ACK_LIMIT Cbox CSR 4 25 defined 5 34 SYSBUS_FORMAT Cbox CSR 4 21 SYSBUS_MB_ENABLE Cbox CSR 4 23 defined 5 34 operation 2 32 SYSBUS_VIC_LIMIT...

Page 356: ...program counter logic VREF values for 9 3 VSS signal pin list 3 16 W WAIT_BiSI reset machine state 7 18 WAIT_BiST reset machine state 7 18 WAIT_ClkFwdRst0 reset machine state 7 18 WAIT_ClkFwdRst1 reset machine state 7 18 WAIT_INTERRUPT reset machine state 7 19 WAIT_NOMINAL reset machine state 7 17 WAIT_RESET reset machine state 7 18 WAIT_SETTLE reset machine state 7 17 WAKEUP interrupt 6 14 WAR el...

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