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CM1K Hardware User’s Manual

Architecture of the CM1K

CM1K is a high-performance pattern recognition chip featuring a network of 1024 neurons operating in parallel.

Also, the chip embeds a recognition engine ready to classify a digital signal received directly from a sensor.

The CM1K is composed of the following modules

Top control logic (NSR and RSR registers, Ready and Busy control signals)

Clusters of 16 neurons

Recognition stage (optional usage)

I2C slave (optional usage)

2.1

Top Control logic

Synchronize communication between the clusters of neurons, the recognition state machine and the I2C

slave.

Inter-module communication is made though a bi-directional parallel bus of 25 wires: data strobe (DS),

read/write (RW_), 5-bit register (REG), 16-bit data (DATA), ready (RDY)

Inter-neuron communication also uses two additional lines indicating the global status of the neural

network: identified recognition (ID), uncertain recognition (UNC).

Communication with external control unit can be made through the same parallel bus or the serial i2C

bus.

Summary of Contents for CM1K

Page 1: ...CM1K hardware User s Manual Version 2 5 0 Revised 03 20 2013...

Page 2: ...leteness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice This Product is not designed manufactured or inte...

Page 3: ...asting 18 3 5 2 Learn a vector 19 3 5 3 Recognize a vector 21 3 5 4 Reading the number of committed neurons 24 3 5 5 Reading the contents of the neurons 25 3 5 6 Reading the contents of a single speci...

Page 4: ...Registers Access Latency 44 7 1 1 Commands executing in multiple cycles LCOMP CAT and DIST 44 7 1 2 Multiple read write to the COMP register 45 7 2 Typical Timings Constraints 45 7 2 1 Learn a vector...

Page 5: ...neurons with same distance and category 58 12 3 07 03 2012 Erroneous ID_line and NSR value when more than 416 neurons committed 59 13 What is new in this manual 61 13 1 1 Revision 03 20 13 61 13 1 2...

Page 6: ...s Recognition stage optional usage I2C slave optional usage 2 1 Top Control logic Synchronize communication between the clusters of neurons the recognition state machine and the I2C slave Inter module...

Page 7: ...through of 15 registers Most operations execute in 1 clock cycle except for Write LCOMP Write CAT Read CAT and Read DIST which can take up to 19 clock cycles Daisy chain connectivity between the neuro...

Page 8: ...vector on the digital input bus of the chip This paragraph gives a brief overview of the neural network functionality For a detailed description of the neuron s behavior and their interactions please...

Page 9: ...t that these neurons are in disagreement with its classification This line is an in out line because used as an input during the execution of certain Write register The neurons sample a new command on...

Page 10: ...tate mode i e 0xFFFF During the second and last cycle of the Write LCOMP the firing neurons output their category value and DATA represents their resulting bit per bit AND combination i e 0x0001 If th...

Page 11: ...euron s behavior and their interactions please refer to the manual CogniMem Technology Reference Guide Description Addr 8 bit Normal mode SR mode Data 16 bit Default NSR Network Status Register Bit 1...

Page 12: ...er using the new distance between the component value and the neuron s memory value with same index the norm is defined by bit 7 of the GCR If the component index is zero the distance register is rese...

Page 13: ...only and reserved to indicate if the neuron is degenerated or not Bits 14 0 represent the category value assigned to the pattern learned by the neuron This value can range between 0 and 32766 0x7FFE R...

Page 14: ...d do not draw current from the pull up resistors 0x0E W n a FORGET Clear the neuron s category register resetting its status to idle The value written to this register is discarded Note that the neuro...

Page 15: ...memory index is incremented by 1 after a Write Comp or is reset to 0 after a Write LCOMP Component 255 Takes the value of the next Write Comp or Write LCOMP The memory index is reset to 0 Can only be...

Page 16: ...ging the RTL neuron in chain Memory cell index change Normal mode Save and Restore mode Write COMP Index 1 Index 1 Write LCOMP Index 0 Write INDEXCOMP Index k Index k Write TESTCOMP Index 1 Write NSR...

Page 17: ...ory to all the neurons Useful for test routines Writing the value 0 to this register is equivalent to writing the FORGET register except that it does not reset the neuron count 0x09 n a W 0x0000 3 4 2...

Page 18: ...ed of up to 256 components of 8 bit value 1 Write Context optional If the new vector must be associated to a context different than the current value of the Global Context or if the distance norm code...

Page 19: ...components and then writing its category value Optionally the PowerSave register can be written to set the data lines in tri state mode so they do not draw current If this combined information vector...

Page 20: ...its AIF to a smaller value during training and its response should be weighted differently than the response of another firing neuron which is not degenerated Example Let s take the example of an inpu...

Page 21: ...lculated between the input vector and its vector in memory is less than its influence field In either cases the response of the neurons can be accessed by a succession of Read DIST followed by Read CA...

Page 22: ...ater than 0x8000 or 32768 bit 15 1 you have a warning that the neuron is degenerated The real category value can be obtained by masking bit 15 with 0 AND with 0x7FFF The degenerated flag simply indica...

Page 23: ...st of a mistake the requirements for a minimum throughput minimum false negative etc Example 1 Let s take the example of an input vector equal to a series going from 00 to 99 This vector has a length...

Page 24: ...number of committed neurons in the chain EXCEPT when the chain is full meaning that all the neurons are committed in which case CM_NCOUNT 0xFFFF If N the number of CM1K chips daisy chained in the sys...

Page 25: ...gister and not to the CM_LCOMP register Remark 2 If it is known that all neurons hold a pattern with only M significant components with M 256 the number of Read COMP can be limited to M thus speeding...

Page 26: ..._and_Restore mode and pointing to the first neuron of the chain In order to point to the i th neuron in the chain i 1 consecutives Read CM_CAT are necessary You can then read the i th neuron s compone...

Page 27: ...emark 3 If you intend to use the newly committed neurons as a KNN classifier as opposed to the default RBF classifier writing the AIF register is not necessary since it will not be used by the KNN cla...

Page 28: ...Write CM_NCR x2 Write CM_AIF x135 Write CM_CAT x33 For i 0 i 100 i Write CM_COMP Vector2 i Write CM_NCR x2 Write CM_AIF x456 Write CM_CAT x22 Write CM_NSR LastNSR Write CM_GCR LastGCR 3 5 8 Typical o...

Page 29: ...case V_DATA is not accumulated directly to the FIFO but rather integrated spatially per blocks of pixels The calculated average value per block is then accumulated to the FIFO This operation is calle...

Page 30: ...ng that the firing neurons do not recognize the same category Remark The output register RTCAT correspond to the category of the best match Additional categories can be obtained by stopping the recogn...

Page 31: ...is case the chip extracts a signature vector from a region of interest in the video frame as the video signal as it is received The region of interest is described by the registers described below Des...

Page 32: ...2 Move the region of interest Move the region of interest to the location 10 12 and learn it as category 33 Sequence Write CM_LEFT 10 Write CM_TOP 12 Write CM_RSR 1 Write CM_CAT 33 4 2 3 Recognize the...

Page 33: ...the negative edge of the system clock when the CAT_VALID signal The only time available to receive and execute an external command is between the fall of the CAT_VAL pulse and the next rise of F_FV I...

Page 34: ...data for its internal registers thus requiring two 8 bit transfers per read or write command A stop bit Definition SlaveID 0x4A SlaveID_Wr 0x94 SlaveID_Rd 0x95 5 1 Write sequence Step Master Slave 1 A...

Page 35: ...r The master sends an acknowledge bit after the eight bit transfer 8 The master clocks out the upper byte of the 16 bit data read from the register The master sends an acknowledge bit after the eight...

Page 36: ...CM1K Hardware User s Manual 36 Stop sequence STOP signal NACK signal The B_BSY signal is the CM1K is pulled high during the processing of an I2C request...

Page 37: ...us is released with a stop bit Only the master can generate the start and stop bits 5 4 2 Start Bit The start bit is defined as a HIGH to LOW transition of the data line while the clock line is HIGH 5...

Page 38: ...able Clock and Reset G_CLK Input System clock G_RESET_ Hardware reset CS_ Input Enable chip activity Parallel bus DS Bidir Data strobe line R W_ Bidir Read Write REG 0 4 Bidir Register DATA 0 15 Bidir...

Page 39: ...em clock pass through must be accurate 1 It must be pulled down on a negative edge of G_CLK when the external data strobe DS is pulled up at the latest 2 It must be released on the negative edge of th...

Page 40: ...n DS is high and RW is low At the end of a read operation RW high and RDY rising DATA is the 16 bit value of the selected register It can be read on or after the rising edge of CM_RDY after the fall o...

Page 41: ...logic of the chip is activate it is possible to overwrite the settings of the DATA lines through the RSR register In that case the RT_CAT register is latched on the DATA lines at each CAT_VAL pulse 6...

Page 42: ...ns If changed dynamically the status of this pin must be changed at the negative edge of V_CLK This pin is connected to an internal pull up so it is enabled by default For power savings consideration...

Page 43: ...TA output bus This strobe lasts one clock cycle 6 7 UI2C serial bus The CM1K I2C slave controller can receive commands from an external I2C master controller operating at a speed of 100 or 400 Kbit pe...

Page 44: ...TESTCAT Test Category 1 0x0A NID Neuron Identifier 1 1 0x0B GCR Global Context Register 1 1 0x0C RESETCHAIN 1 0x0D NSR Network Status Register 1 1 0x0F FORGET Clear the neurons 1 0x0F NCOUNT Committe...

Page 45: ...nstraints In the example below a vector of 8 components is learned and then recognized The resolution of the diagrams does not allow reading the DATA values of the components and the category but this...

Page 46: ...remains high the DS pulse triggers a Read CAT The RDY signal is pulled down for 19 cycles which is the duration of the Search and Sort looking for the firing neuron with a distance register equal to 0...

Page 47: ...RDY signal is pulled down for 18 cycles which is the duration of the Search and Sort looking for the firing neuron with the smallest distance value This distance is equal to 00 indicating an exact ma...

Page 48: ...arn and recognize vector data transmitted by the control unit through the serial bus I2C_CLK and I2C_DATA If the RECO_EN pin is set to 1 vector data can be transmitted through the digital input bus an...

Page 49: ...to monitor the recognition status the parallel control lines CAT_VAL and DIST_VAL output by the first chip can be sufficient outputs 8 2 2 Control through serial bus b If an application requires a lo...

Page 50: ...and b 1 in config e I2C_EN 0 in config a and e 1 in config b 0 RECO_EN Optional in config a and b 1 in config e 0 in config a and b 1 in config e V_CLK V_FV V_DATA Used if RECO_EN 1 n a V_EN Used if...

Page 51: ...CAT_VAL B_BSY VCC S_CHIP RSVD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1...

Page 52: ...robe line 54 VCCIO IO power supply line 3 3 v 55 VCC Core power supply 1 2v 56 VCC Core power supply 1 2v 57 GND Ground line 58 DIST_VAL Output Distance valid line 59 VCCIO IO power supply line 3 3 v...

Page 53: ...ata strobe line G_CLK Input 8 Master clock Up to 27 Mhz for a single chip Up to 13 5 Mhz for a multiple chip configuration G_Reset_ 3 Global reset_low line GND 57 90 Grond line I2C_EN Input PU 5 I2C e...

Page 54: ...61 6 6 70 72 83 85 89 92 94 9 8 Core power supply 1 2v VCCIO 2 7 9 12 32 34 39 44 48 5 1 54 59 64 68 71 74 77 7 9 82 86 IO power supply line 3 3 v 9 2 Mechanical specifications Die size 8 mm x 8 mm Pr...

Page 55: ...eurons the reco_logic and the i2c slave controller of the chip It is pulled low by default letting the clock run continuously Pulling up the the CS_ line when the CM1K is unused reduces considerably i...

Page 56: ...am in very low power As long as the core remains at 1 2 volts the neurons content is kept How fast can the part wake and become ready after STDBY is deasserted o Next clock cycle How much power does t...

Page 57: ...and the CM1K chip ZISC and CM1K comparative chart Feature ZISC78 CM1K Number of neurons per chip 78 1024 Neuron memory size 64 bytes 256 bytes Distance register 16 bit 16 bit Category value 15 bit 15...

Page 58: ...gory the readout of the Category register will exclude them all at once from the next search and sort Note that if you are interested in surveying the histogram of the distances and a probability dens...

Page 59: ...han 416 neurons committed The 1024 neurons of the CM1K are arranged in 64 clusters of 16 neurons connected in parallel through the same parallel neuron bus as the one used to connect multiple CM1K chi...

Page 60: ...is different from 0xFFFF the ID_ line should be pulled down and remain as such until the first cycle of the next Write LCOMP command while DS is high This will ensure that the NSR register of the chi...

Page 61: ...o clusters of neurons in the CM1K chip 13 3 Revision from 02 17 2012 UNC_ line must not be driven New FAQ chapter 13 4 Revision from 11 1 2011 New power savings tip in chapter 9 Correction of an erron...

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