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unless this bit is set. If the receive queue is full and the core receives a new word, an overrun condi-
tion will occur. The received data will be discarded and the Overrun (OV) bit in the Event register will
be set.
The core will also detect underrun conditions. An underrun condition occurs when the core is
selected, via SPISEL, and the SCK clock transitions while the transmit queue is empty. In this sce-
nario the core will respond with all bits set to ‘1’ and set the Underrun (UN) bit in the Event register.
An underrun condition will never occur in master mode. When the master has an empty transmit
queue the bus will go into an idle state.
24.2.4 Clock generation
The core only generates the clock in master mode, the generated frequency depends on the system
clock frequency and the Mode register fields DIV16, FACT, and PM. Without DIV16 the SCK fre-
quency is:
With DIV16 enabled the frequency of SCK is derived through:
Note that the fields of the Mode register, which includes DIV16, FACT and PM, should not be
changed when the core is enabled.
24.2.5 Slave operation
When the core is configured for slave operation it does not drive any SPI signal until the core is
selected, via the SPI_SEL input, by a master. If the core operates in SPI mode when SPI_SEL goes
low the core configures SPI_MISO as an output and drives the value of the first bit scheduled for
transfer. If the core is configured into 3-wire mode the core will first listen to the SPI_MOSI line and
when a word has been transferred drive the response on the SPI_MOSI line. If the core is selected
when the transmit queue is empty it will transfer a word with all bits set to ‘1’ and the core will report
an underflow.
Since the core synchronizes the incoming clock it will not react to transitions on SPI_SCK until two
system clock cycles have passed. This leads to a delay of three system clock cycles when the data out-
put line should change as the result of a SPI_SCK transition. This constrains the maximum input
SPI_SCK frequency of the slave to (system clock) / 8 or less. The controlling master must also allow
the decreased setup time on the slave data out line.
The core can also filter the SCK input. The value of the PM field in the Mode register defines for how
many system clock cycles the SCK input must be stable before the core accepts the new value. If the
PM field is set to zero, then the maximum SCK frequency of the slave is, as stated above, (system
clock) / 8 or less. For each increment of the PM field the clock period of SCK must be prolonged by
two times the system clock period as the core will require longer time discover and respond to SCK
transitions.
24.2.6 Master operation
When the core is configured for master operation it will transmit a word when there is data available
in the transmit queue. When the transmit queue is empty the core will drive SPI_SCK to its idle state.
If the SPI_SEL input goes low during master operation the core will abort any active transmission and
SCKFrequency
AMBAclockfrequency
4
2
FACT
–
PM
1
+
---------------------------------------------------------------------
=
SCKFrequency
AMBAclockfrequency
16
4
2
FACT
–
PM
1
+
--------------------------------------------------------------------------------
=
