GR716-DS-UM, May 2019, Version 1.29
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GR716
ter itself (for N-Chars and Time-codes) to be transmitted are presented to the low-level transmitter
which is located in a separate clock-domain.
The transmitter logic in the host clock domain decides what character to send next and sets the proper
control signal and presents any needed character to the low-level transmitter as shown in figure 50.
The transmitter sends the requested characters and generates parity and control bits as needed. If no
requests are made from the host domain, NULLs are sent as long as the transmitter is enabled. Most of
the signal and character levels of the SpaceWire standard is handled in the transmitter. External LVDS
drivers are needed for the data and strobe signals.
A transmission FSM reads N-Chars for transmission from the transmitter FIFO. It is given packet
lengths from the DMA interface and appends EOPs/EEPs and RMAP CRC values if requested. When
it is finished with a packet the DMA interface is notified and a new packet length value is given.
33.3.3 Receiver
The receiver detects connections from other nodes and receives characters as a bit stream recovered
from the data and strobe signals by the GRSPW2_PHY module, which presents it as a data and data-
valid signal. The receiver and GRSPW2_PHY are located in a separate clock domain which runs on a
clock outputed by the GRSPW2_PHY.
The receiver is activated as soon as the link interface leaves the error reset state. Then after a NULL is
received it can start receiving any characters. It detects parity, escape and credit errors which causes
the link interface to enter the error reset state. Disconnections are handled in the link interface part in
the tx clock domain because no receiver clock is available when disconnected.
Received Characters are flagged to the host domain and the data is presented in parallel form. The
interface to the host domain is shown in figure 51. L-Chars are the handled automatically by the host
domain link interface part while all N-Chars are stored in the receiver FIFO for further handling. If
two or more consecutive EOPs/EEPs are received all but the first one are discarded.
33.3.4 Dual port support
With dual ports the transmitter drives an additional pair of data/strobe output signals and one extra
receiver is added to handle a second pair of data/strobe input signals.
Transmitter Clock Domain
Host Clock Domain
Transmitter
D
S
Send Time-code
Send FCT
Send NChar
Time-code[7:0]
NChar[8:0]
Figure 50.
Schematic of the link interface transmitter.
Receiver Clock Domain
Host Clock Domain
Receiver
D
DV
Got Time-code
Got FCT
Got NChar
Time-code[7:0]
NChar[7:0]
Figure 51.
Schematic of the link interface receiver.
Got EEP
Got EOP