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CMS80F731x Reference Manual
3.2
External Reset
External reset refers to a reset signal from an external port (NRST) that resets the chip after being input by a Schmitt trigger.
If the NRST pin remains low above about 16us (internal LSI clock sampled with 3 rising edges) during operating voltage range
and stable oscillation, a reset is requested. After the internal state is initialized and reset state changes to "1", it takes 16ms of
settling time for the internal RESETB signal to become "1", and the program starts at vector address 0000H.
The process of reconfiguring the chip during Stabilization Time is the same as the configuration process for power-on reset.
The external reset pin NRST and its pull-up resistor enable, configured via CONFIG.
3.3
LVR Low-voltage Reset
A low-voltage reset (LVR) function is integrated inside the chip, and when the system voltage VDD falls below the LVR
voltage, the LVR is triggered and the system resets. The voltage point that triggers the reset can be set in CONFIG.
The LVR module detects that the VDD <V
LVR
, i.e. the LVR output remains low for about 16us or more (the internal LSI clock
samples 3 rising edges) and requests a reset. In sleep mode (STOP) mode, lvr low-voltage reset disables.
The LVR low-voltage reset timing diagram is shown in the following figure:
V
LVR
VDD
Internal
RESETB
V
LVR
3 raise sample
LSI
(125KHz)
~
~
Stabilization Time 16ms
Main Program
Release
The process of reconfiguring the chip during Stabilization Time is the same as the configuration process for power-on reset.
