Cmsemicon CMS80F731 Series, Reference Manual

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1.00
CMS80F731x Reference Manual
17.5.6
PWM Clock Divide Control Register PWMnDIV (n=0-5)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMnDIV -- -- -- -- -- PWMnDIV2 PWMnDIV1 PWMnDIV0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Registers PWMnDIV (n=0-5) Address: F12AH, F12BH, F12CH, F12DH, F12EH, F12FH.
Bit7~Bit3 -- Reserved, must be 0.
Bit2~Bit0 PWMnDIV<2:0>: PWM channel n clock divider control bit;
000= Fpwmn-PSC/2;
001= Fpwmn-PSC/4;
010= Fpwmn-PSC/8;
011= Fpwmn-PSC/16;
100= Fpwmn-PSC;
Other = Fsys (system clock);
(PSC is the clock after prescale).
17.5.7
PWM Data Loading Enable Control Register PWMLOADEN
F129H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMLOADEN -- -- PWM5LE PWM4LE PWM3LE PWM2LE PWM1LE PWM0LE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit6 -- Reserved, must be 0.
Bit5~Bit0 PWMnLE: Data loading enable bits (n=0-5) of PWM channel n (hardware clearing is completed
after loading);
1= Enable load cycle, duty cycle data (PERIODn, CMPn, CMPDn).
0= Writing 0 is invalid.
17.5.8
PWM Output Polarity Control Register PWMPINV
F122H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMPINV -- -- PWM5PINV PWM4PINV PWM3PINV PWM2PINV PWM1PINV PWM0PINV
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit6 -- Reserved, must be 0.
Bit5~Bit0 PWMnPINV: PWM channel n output polarity control bit (n=0-5);
1= Reverse output;
0= Normal output.