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CMS80F731x Reference Manual
14.3 Feature Description
The BRT has a 16-bit increment counter, the clock is derived from the pre-division circuit, the pre-division clock is determined
by the timer pre-division select bit BRTCKDIV, and the initial value of the counter is loaded by {BRTDH, BRTDL}.
When the timer enable bit BRTEN=1 is turned on, the counter starts working. When the value of the 16-bit counter is equal
to FFFFH, the BRT counter overflows. After the overflow, the initial value of the count is automatically loaded into the counter
and then the count is re-counted.
The overflow signal of the BRT counter is specially provided to the UART module as a clock source for the baud rate, and
there is no interrupt when overflowing, and there is no corresponding interrupt structure. BrT in debug mode, its clock does not
stop, if the UART module has begun to send or receive data, even if the chip into a suspended state, the UART will complete
the entire process of sending or receiving.
BRT timer overflow rate:
BRTov=
Fsys
(
65536-{BRTDH,BRTDL}
)
×2
BRTCKDIV
