BAT32G1x9 user manual | Chapter 20 Serial interface IICA
802 / 1149
Rev.1.02
20.6 Timing diagram
In I2C-bus mode, the master device selects a slave device for a communication object from multiple slave devices
by outputting an address to the serial bus. The master device sends a TRCn bit (bit3 of the IICA status register n
(IICSn)) that indicates the direction of data transmission after the slave address Begin serial communication with the
slave. The timing diagram of data communication is shown in FIG 20-30and FIG 20-31.
The shift of the IICA shift register n (IICAn) is carried out synchronously with the falling edge of the serial clock
(SCLAn), and the transmit data is transmitted to the SO latch, in MSB Prioritize outputting data from the SDAAn pin.
Take the data from the SDAAn pin input to the IICAn on the rising edge of the SCLAn.
Note: n=0,1
