BAT32G1x9 user manual | Chapter 4 Clock generation circuit
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Rev.1.02
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Continuous operation mode
In continuous operation mode, the high-speed internal oscillating clock frequency correction action is
carried out all the time. The FCMD bit of the HOCOFC register is set to 0, which is a continuous operation
mode.
The FCST bit of the HOCOFC register is set to 1 when the high-speed internal oscillator clock
frequency correction action begins. Similarly, the high-speed internal oscillation clock frequency correction
action stops when the FCST bit is set to 0.
After the high-speed internal oscillator clock frequency correction action, the count starts at the rising
edge of the reference clock (fSUB/
2 9
) and stops counting on the rising edge of the next reference clock
(fSUB/2
9
). (Frequency measurement phase).
The count value is then compared to the expected value and the correction values are adjusted as
described below. (Frequency Correction Phase)
When the count value is larger than expected: The correction value is -1
Count value is hours longer than expected: Correction value +1
When the count value is within the expected value: the correction value is maintained (the high-
speed internal oscillation clock frequency correction ends)
When the FCIE bit of the HOCOFC register is set to 1, an interrupt is generated when the high-speed
internal oscillator clock frequency correction is completed. In continuous operation mode, the high-speed
internal oscillating clock frequency correction function repeats the frequency measurement phase and the
frequency correction phase until the high-speed internal oscillating clock frequency correction function is
stopped.
Figure 4-26is a timing diagram of the continuous motion mode.
Figure 4-26 Sequential diagram of continuous motion mode
Reference
clock
(fsub/2^9)
CRST
(Action enabling
position)
20 bit count
register
"0000000B"
Correction
value
[6:0]
"0000001B"
"0000010B"
"0000010B"
+
１
+
１
keep
Intermediate
value of counter
keep
CRST clear: software clear.
CRMD
(Action mode bit)
Continuous action mode "0"
High speed internal
frequency correction
completion interrupt
Interrupt generation: when CRIE bit is 1, fHOCO pulse with
1 cycle width will be output when correction is completed.
