BAT32G1x9 user manual | Chapter 4 Clock generation circuit
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Rev.1.02
4.6.7
Conditions before clock oscillation stops
The register flag settings used to stop clock oscillation (invalid external clock input) and the conditions before stopping are
as follows.
Table 4-8
Conditions and flag settings before clock oscillation stops
clock
Condition before clock stop (external clock input is
invalid)
Flag setting for SFR
registers
High-speed internal
oscillator clock
MCS=1 or
CLS=1
(The CPU
runs on a clock other than the high-speed internal oscillator
clock).
HIOSTOP=1
X1 clock
MCS=0 or
CLS=1
(The CPU
runs on a clock other than the high-speed system clock).)
MSTOP=1
External master system
clock
XT1 clock
CLS=0
(The CPU
runs on a clock other than the sub-system clock).
XTSTOP=1
External subsystem
clock
