AN201
Rev 1.5 | 60/91
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Configure the FOSC<2:0> in the Configuration Word register CONFIG as the LP or XT mode.
It enters the two-speed start-up mode after the steps below.
Power-on reset (POR) and start power-on timer (PWRT).
Timer ends (if it is enabled) or wake-up from sleep.
If the external clock oscillator is configured as a mode other than the LP and XT mode, the two-speed start-up will be disabled
since the external clock oscillation does not require any stabilization time after POR or exiting from sleep.
5.5.2 Two-Speed Start-up Sequence
1.
Wake-up from sleep or power-on reset.
2.
Execute instructions using the internal oscillator at the frequency set in the IRCF<2:0> bit of the OSCCON register.
3.
The OST instruction counts 1024 clock cycles.
4.
The OST is timeout waiting for the falling edge of the internal oscillator.
5.
OSTS is set to 1.
6.
The system clock keeps low until the next falling edge the new clock arrives (LP or XT mode).
7.
The system clock is switched to the external clock source.
5.6 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue operating in the event of an oscillator failure.
FSCM can detect the oscillator failure at any time after the oscillator start-up timer (OST) expires. FSCM can be enabled by
setting the FCMEN bit in the configuration word register
（
UCFG1
）
to 1. FSCM can be used for all external oscillator modes (LP,
XT and EC).
Figure 16. FSCM Schematic
5.6.1 Fail-Safe Detection
The FSCM module detects the oscillator fault by comparing the external oscillator with the FSCM sampling clock. LFINTOSC
divided by 64 is the sampling clock. See Figure 16 for details . There is a latch inside the fault detector. On each falling edge of
External Clock
（
LP/XT/EC
）
Q
Q
SET
CLR
S
R
LFINTOSC
～
32KHz
Frequency Divider
/64
Clock error
signal
Edge triggered
register
Sampling clock
generation
