CMT2380F17
Rev0.1 | 41/347
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SCLK
FCSB
SDA
X
X
FIFO write data
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
X
FIFO write data
CSB
> 1 SCLK cycle
> 4 us
> 2 us
> 2 us
> 1 SCLK cycle
Figure 4-8. SPI Write FIFO Timing
The transceiver provides enriched FIFO-related interrupt sources helping for efficient operation of the chip. The Rx and
Tx-related FIFO interrupt timing is shown in the figure below.
1
0
3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
27
26
29
28
31
30
EMPTY
FULL
RX_FIFO_NMTY
RX_FIFO_TH
RX_FIFO_FULL
Sync
1
0
3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
27
26
29
28
31
30
RX DATA
Noise
Noise
SYNC_OK
RX FIFO ARRAY
RX_FIFO_OVF
(FIFO_TH = 16)
RX_FIFO_WBYTE
Figure 4-9. Transceiver RX FIFO Interrupt Timing Schematic
1
0
3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
27
26
29
28
31
30
EMPTY
FULL
TX_FIFO_NMTY
TX_FIFO_TH
TX_FIFO_FULL
Sync
1
0
3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
27
26
29
28
31
30
TX DATA
Prefix
0
FIFO ARRAY
(FIFO_TH = 16)
Pream
Figure 4-10. Transceiver TX FIFO Interrupt Timing Schematic
4.11.3
Transceiver Operating Status, Timing, and Power Consumption
Startup Timing
After the transceiver is powered up on RF-VDD, generally it takes about 1 ms for POR release. The crystal starts after POR
release. The startup time defaults to N ms depending on characteristics of the crystal itself. After startup, it needs to wait for a
period of time for crystal stabilization then to start working. The default stabilization time is set as 2.48ms by default. The time can
Summary of Contents for CMT2380F17
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Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
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