CMOSTEK CMT2380F17, Manual

Page: 200 / 347

CMT2380F17
Rev0.1 | 200/347
www.cmostek.com
18 Serial Port 0 (UART0)
The serial port 0 of CMT2380F17 support full-duplex transmission, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a
previously received byte has
been read from the register. However, if the first byte still hasn’t been read by the
time reception of the second byte is complete, one of the bytes will be lost. The serial port receive and
transmit registers are both accessed at special function register S0BUF. Writing to S0BUF loads the transmit
register, and reading from S0BUF accesses a physically separate receive register.
The serial port can operate in 5 modes: Mode 0 provides synchronous communication while Modes 1, 2,
and 3 provide asynchronous communication. The asynchronous communication operates as a full-duplex
Universal Asynchronous Receiver and Transmitter (UART), which can transmit and receive simultaneously
and at different baud rates. Mode 4 in UART0 supports SPI master operation which data rate setting is same
as Mode 0.
Mode 0: 8 data bits (LSB first) are transmitted or received through RXD0. TXD0 always
outputs the shift clock. The baud rate can be selected to 1/12 or 1/4 the system clock
frequency by URM0X3 setting in S0CFG register. In MG82F6D17 , the clock polarity of serial
port Mode 0 can be selected by software. It is decided by P3.1 state before serial data shift in
or shift out. Figure 18
–4
and Figure 18
–5
show the clock polarity waveform in Mode 0.
Mode 1: 10 bits are transmitted through TXD0 or received through RXD0. The frame data
includes a start bit (0), 8 data bits (LSB first), and a stop bit (1), as shown in Figure 18
–1
. On
receive, the stop bit would be loaded into RB80 in S0CON register. The baud rate is variable.
D1 D2 D3 D4 D5 D6 D7
Mode 1
Start D0 Stop
8-bit data
Figure 18-1. Mode 1 Data Frame

Mode 2 Mode 2: 11 bits are transmitted through TXD0 or received through RXD0. The frame data
includes a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1), as shown in
Figure 18
–2. On Transmit, the 9th data bit comes from TB80 in S0CON register can be assigned the
value of 0 or 1. On receive, the 9th data bit would be loaded into RB80 in S0CON register, while the stop
bit is ignored. The baud rate can be configured to 1/32 or 1/64 the system clock frequency.
D1 D2 D3 D4 D5 D6
Mode 2, 3
Start D0 Stop D8 D7
9-bit data
Figure 18-2. Mode 2, 3 Data Frame

Mode 3
：
Mode 3 is the same as Mode 2 except the baud rate is variable.
In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. In
Mode 0, reception is initiated by the condition RI0=0 and REN0=1. In the other modes, reception is initiated by
the incoming start bit with 1-to-0 transition if REN0=1.