CMOSTEK CMT2210A Design Manualline Download Page 2

 
 

AN107 

 

 

Rev 1.0 | Page 2/10

 

 

www.hoperf.com 

Notes:

 

1. 

L2 is the VCO tank inductor. The VCO oscillates at the frequency which is 2x of the RF frequency. In order to 

suppress  the  spurious emission  and minimize phase noise, a high-Q  inductor  is  used.  For a  433.92  MHz 

design it is suggested to use a 22 nH inductor with Q > 25 at 800 MHz. For a 315 MHz design it is suggested to 

use a 33 nH inductor with Q > 25 at 600 MHz.

 

 

2. 

L1 and C4 transform the impedance seen at the RFIN pin to the antenna impedance. 

3. 

C1 and C2 are the power supply decoupling capacitors. C1 is an optional decoupling capacitor depending on 

the power supply purity level

4. 

The crystal oscillator consists of an extent crystal X1 and two loading capacitors (C5 and C6). The Total load 

capacitance  seen  between  the crystal  terminals  should  equal  C

L

  for  the  crystal to oscillate at the specified 

frequency.

   

C

L

 =

C5 

*

 

 

C6 

C5 + C6 

+

Δ

2

 

 

The parasitic capacitance 

Δ

C is constituted by pin input capacitance and PCB stray capacitance. The ESR of 

the crystal should be within 60 Ω in order to ensure a reliable start

-up. The total tolerance is ±20 ppm typically, 

which include initial tolerance, crystal loading, aging, and temperature dependence. The acceptable tolerance 

depends on RF frequency and channel spacing/bandwidth. 

5. 

An external clock source can easily be used in place of a crystal oscillator. The incoming clock signal is 

recommended to have a peak-to-peak swing in the range of 300 mV to 700 mV and AC-coupled to the XTAL 

pin. 

6. 

P1 is 

a SMA connector for a 50 Ω antenna

7. 

The DOUT pin outputs the

 

demodulated data. 

8. 

The test points (TP1/2/3/4/5 connected to VDD, GND, SCL, SDA, and CSB respectively) must be reserved if 

EEPROM programming is required. The CSB, SDA and SCL should be left un-connected if they are not used. 

9. 

By default, an active low reset signal is generated by the internal POR and output via the nRSTO pin. It can be 

used to reset the external MCU if it is required. The CMT2210A can provide a configurable system clock output 

from the CLKO pin to drive the external device. The nRSTO and CLKO should be left un-connected if they are 

not used. 

10.  Pin descriptions of the CMT2210A, and the BOM for CMT2210A application are shown in Table 1 and Table 2.

 

 

 

 

Summary of Contents for CMT2210A

Page 1: ...reless applications The chip is part of the CMOSTEK NextGenRFTM family which includes a complete line of transmitters receivers and transceivers To give the CMT2210A schematic design guidelines an exa...

Page 2: ...d be within 60 in order to ensure a reliable start up The total tolerance is 20 ppm typically which include initial tolerance crystal loading aging and temperature dependence The acceptable tolerance...

Page 3: ...ce clock input 10 nRSTO O Active low power on reset output to reset an external MCU 11 VCOP IO VCO tank connected to an external inductor 12 VCON 13 15 GND I Ground 14 RFIN I RF input 16 VDD I Power s...

Page 4: ...transmission line is in proportion to the thickness of the PCB and the distance between the routing and grounding around it It is in inverse proportion to the width thickness of the routing and the di...

Page 5: ...ignal routing should be smooth to avoid the impedance variation on the transmission lines which will result in RF signal reflection and performance inconsistency in mass production Wherever possible t...

Page 6: ...d as this may shift the crystal DC operating point and result in duty cycle variation The XTAL circuit is shown in the figure below Figure 5 XTAL Circuit Layout 3 1 4 Digital Signals Routing The digit...

Page 7: ...his port To minimize the radiation from the VCO circuit and maintain the high Q factor of the VCO tank L2 should be placed as close as possible to the CMT2210A The VCO tank is surrounded by a solid gr...

Page 8: ...us ground plane metallization as possible 2 Place a series of ground vias along the PCB edges if possible The maximum distance between the vias should be less than 10 This is required to reduce the PC...

Page 9: ...AN107 Rev 1 0 Page 9 10 www hoperf com 4 Document Change List Table 3 Document Change List Rev No Chapter Description of Changes Date 0 9 Initial released version 2014 06 14 1 0 2014 06 30...

Page 10: ...is assumed for inaccuracies and specifications within this document are subject to change without notice The material contained herein is the exclusive property of CMOSTEK and shall not be distribute...

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