Schematic Diagrams
PROCESSOR/ RESERVED B - 9
B.Sch
e
m
a
tic D
iag
rams
PROCESSOR/ RESERVED
VREF_CH_A_DIMM
R360
*0_04
R358
*0_04
Q34
*AO3402L
G
D
S
R359
*1K_04
Q33
*AO3402L
G
D
S
R361
*1K_04
DRAMRST_CNTRL 3,14
MVREF_DQ_DIMMA 9
DRAMRST_CNTRL
MVREF_DQ_DIMMB 10
VREF_CH_B_DIMM
RESE
RVE
D
U21E
PZ98827-364B-01F
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL26
CFG[3]
AL27
CFG[4]
AK26
CFG[5]
AL29
CFG[6]
AL30
CFG[7]
AM31
CFG[8]
AM32
CFG[9]
AM30
CFG[10]
AM28
CFG[11]
AM26
CFG[12]
AN28
CFG[13]
AN31
CFG[14]
AN26
CFG[15]
AM27
CFG[16]
AK31
CFG[17]
AN29
RSVD34
AM33
RSVD35
AJ27
RSVD38
J16
RSVD42
AT34
RSVD39
H16
RSVD40
G16
RSVD41
AR35
RSVD43
AT33
RSVD45
AR34
RSVD56
AT2
RSVD57
AT1
RSVD58
AR1
RSVD46
B34
RSVD47
A33
RSVD48
A34
RSVD49
B35
RSVD50
C35
RSVD51
AJ32
RSVD52
AK32
RSVD30
AE7
RSVD31
AK2
RSVD28
L7
RSVD29
AG7
RSVD27
J15
RSVD16
C30
RSVD15
D23
RSVD17
A31
RSVD18
B30
RSVD20
D30
RSVD19
B29
RSVD22
A30
RSVD21
B31
RSVD23
C29
RSVD24
J20
RSVD37
T8
RSVD6
B4
RSVD7
D1
RSVD8
F25
RSVD9
F24
RSVD11
D24
RSVD12
G25
RSVD13
G24
RSVD14
E23
RSVD32
W8
RSVD33
AT26
RSVD25
B18
RSVD44
AP35
RSVD10
F23
RSVD5
AJ26
VAXG_VAL_SENSE
AJ31
VSSAXG_VAL_SENSE
AH31
VCC_VAL_SENSE
AJ33
VSS_VAL_SENSE
AH33
KEY
B1
VCC_DIE_SENSE
AH27
VCCIO_SEL
A19
RSVD54
AN35
RSVD55
AM35
CFG6
CFG5
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG[6:5]
R75
*1K_04
PCIE Port Bifurcation Straps
R73
*1K_04
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG7
R74
*1K_04
CFG7
3.3V
2,3,11,13,17,22,23,24,25,29,31,34,36,38
CFG2
CFG2
CFG4
CFG Straps for Processor
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
R76
*1K_04
R80
*1K_04
H_CPU_RSVD1
H_CPU_RSVD4
H_CPU_RSVD3
H_CPU_RSVD2
R343
*20mil_04
CFG7
CFG4
CFG2
CFG6
CFG0
CFG5
1.5V
3,6,9,10,20,29,31,34,36
Sandy Bridge Processor 7/7
( RESERVED )
VREF_CH_A_DIMM
VREF_CH_B_DIMM
3.3V
R342
10K_04
H_SNB_IVB#_PWRCTRL
Sheet 8 of 49
PROCESSOR/
RESERVED
Summary of Contents for W350HU
Page 1: ...W350HU W350HV ...
Page 2: ......
Page 3: ...Preface I Preface Notebook Computer W350HU W350HV Service Manual ...
Page 24: ...Introduction 1 12 1 Introduction ...
Page 47: ...Part Lists LCD A 5 A Part Lists LCD Figure A 3 LCD 富士弘 黑色亮面 今皓 Ω 富士弘 頭徑 頭厚 號穴鍍白鎳 頭 Ω 志精 志精 ...
Page 49: ...Part Lists HDD A 7 A Part Lists HDD Figure A 5 HDD 無鉛 無鉛 ...
Page 50: ...Part Lists A 8 A Part Lists ...