Clevo W240HU Series, Service Manual

Page: 57 / 99

Schematic Diagrams
CPU 1/7 (DMI, PEG, FDI) B - 3
B.Sch
e
m
a
tic D
iag
rams
CPU 1/7 (DMI, PEG, FDI)
Sheet 2 of 43
CPU 1/7
(DMI, PEG, FDI)
D P _ T X P 3 [ 1 1]
11/03
D P _ T XN _ 3
D P _ T X P 0 [ 1 1]
C 3 2 4 *0 . 1 u _1 0 V _ X 7R _ 04
D P _ T X P 1 [ 1 1]
D P _ T XP _3
D P _ T X N 1 [ 1 1]
D P _ T X N 0 [ 1 1]
D P _ T XP _1
D P _ T XP _0
C 3 2 9 *0 . 1 u _1 0 V _ X 7R _ 04
C 3 3 0 *0 . 1 u _1 0 V _ X 7R _ 04
D P _ A U X_ N
D P _ A U X_ P
D P _ T XP _2 C 3 2 7 *0 . 1 u _1 0 V _ X 7R _ 04
D P _ T X P 2 [ 1 1]
D P _ T XN _ 2
D P _ A U XN [ 1 1]
D P _ A U XP [ 1 1]
D P _ T XN _ 0
C 3 2 8 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XN _ 1
C 3 3 1 *0 . 1 u _1 0 V _ X 7R _ 04
D P _ T X N 2 [ 1 1]
C 3 2 5 *0 . 1 u _1 0 V _ X 7R _ 04
C 3 2 6 *0 . 1 u _1 0 V _ X 7R _ 04
PC
I EXP
RE
SS
* - GR
AP
HIC
S
DM
I
In
te
l(
R)
F
DI
eD
P
U 3 4A
P Z 98 8 2 7- 36 4 B -0 1 F
D MI _ R X # [ 0 ]
B 2 7
D MI _ R X # [ 1 ]
B 2 5
D MI _ R X # [ 2 ]
A 2 5
D MI _ R X # [ 3 ]
B 2 4
D MI _ R X [ 0 ]
B 2 8
D MI _ R X [ 1 ]
B 2 6
D MI _ R X [ 2 ]
A 2 4
D MI _ R X [ 3 ]
B 2 3
D MI _ T X# [ 0 ]
G2 1
D MI _ T X# [ 1 ]
E 2 2
D MI _ T X# [ 2 ]
F 2 1
D MI _ T X# [ 3 ]
D 2 1
D MI _ T X[ 0]
G2 2
D MI _ T X[ 1]
D 2 2
D MI _ T X[ 3]
C 2 1 D MI _ T X[ 2]
F 2 0
F D I 0 _T X # [ 0 ]
A 2 1
F D I 0 _T X # [ 1 ]
H 1 9
F D I 0 _T X # [ 2 ]
E 1 9
F D I 0 _T X # [ 3 ]
F 1 8
F D I 1 _T X # [ 0 ]
B 2 1
F D I 1 _T X # [ 1 ]
C 2 0
F D I 1 _T X # [ 2 ]
D 1 8
F D I 1 _T X # [ 3 ]
E 1 7
F D I 0 _T X [ 0 ]
A 2 2
F D I 0 _T X [ 1 ]
G1 9
F D I 0 _T X [ 2 ]
E 2 0
F D I 0 _T X [ 3 ]
G1 8
F D I 1 _T X [ 0 ]
B 2 0
F D I 1 _T X [ 1 ]
C 1 9
F D I 1 _T X [ 2 ]
D 1 9
F D I 1 _T X [ 3 ]
F 1 7
F D I 0 _F S Y N C
J 1 8
F D I 1 _F S Y N C
J 1 7
F D I _ I N T
H 2 0
F D I 0 _L S Y N C
J 1 9
F D I 1 _L S Y N C
H 1 7
P E G_ I C OM P I
J 2 2
P E G_ I C O MP O
J 2 1
P E G _R C O MP O
H 2 2
P E G_ R X # [ 0 ]
K 3 3
P E G_ R X # [ 1 ]
M 3 5
P E G_ R X # [ 2 ]
L 3 4
P E G_ R X # [ 3 ]
J 3 5
P E G_ R X # [ 4 ]
J 3 2
P E G_ R X # [ 5 ]
H 3 4
P E G_ R X # [ 6 ]
H 3 1
P E G_ R X # [ 7 ]
G 3 3
P E G_ R X # [ 8 ]
G 3 0
P E G_ R X # [ 9 ]
F 3 5
P E G_ R X# [ 1 0 ]
E 3 4
P E G_ R X# [ 1 1 ]
E 3 2
P E G_ R X# [ 1 2 ]
D 3 3
P E G_ R X# [ 1 3 ]
D 3 1
P E G_ R X# [ 1 4 ]
B 3 3
P E G_ R X# [ 1 5 ]
C 3 2
P E G_ R X [ 0 ]
J 3 3
P E G_ R X [ 1 ]
L 3 5
P E G_ R X [ 2 ]
K 3 4
P E G_ R X [ 3 ]
H 3 5
P E G_ R X [ 4 ]
H 3 2
P E G_ R X [ 5 ]
G 3 4
P E G_ R X [ 6 ]
G 3 1
P E G_ R X [ 7 ]
F 3 3
P E G_ R X [ 8 ]
F 3 0
P E G_ R X [ 9 ]
E 3 5
P E G_ R X [ 1 0 ]
E 3 3
P E G_ R X [ 1 1 ]
F 3 2
P E G_ R X [ 1 2 ]
D 3 4
P E G_ R X [ 1 3 ]
E 3 1
P E G_ R X [ 1 4 ]
C 3 3
P E G_ R X [ 1 5 ]
B 3 2
P E G _ TX # [ 0 ]
M 2 9
P E G _ TX # [ 1 ]
M 3 2
P E G _ TX # [ 2 ]
M 3 1
P E G _ TX # [ 3 ]
L 3 2
P E G _ TX # [ 4 ]
L 2 9
P E G _ TX # [ 5 ]
K 3 1
P E G _ TX # [ 6 ]
K 2 8
P E G _ TX # [ 7 ]
J 3 0
P E G _ TX # [ 8 ]
J 2 8
P E G _ TX # [ 9 ]
H 2 9
P E G_ T X# [ 1 0 ]
G 2 7
P E G_ T X# [ 1 1 ]
E 2 9
P E G_ T X# [ 1 2 ]
F 2 7
P E G_ T X# [ 1 3 ]
D 2 8
P E G_ T X# [ 1 4 ]
F 2 6
P E G_ T X# [ 1 5 ]
E 2 5
P E G _T X [ 0 ]
M 2 8
P E G _T X [ 1 ]
M 3 3
P E G _T X [ 2 ]
M 3 0
P E G _T X [ 3 ]
L 3 1
P E G _T X [ 4 ]
L 2 8
P E G _T X [ 5 ]
K 3 0
P E G _T X [ 6 ]
K 2 7
P E G _T X [ 7 ]
J 2 9
P E G _T X [ 8 ]
J 2 7
P E G _T X [ 9 ]
H 2 8
P E G _ TX [ 1 0 ]
G 2 8
P E G _ TX [ 1 1 ]
E 2 8
P E G _ TX [ 1 2 ]
F 2 8
P E G _ TX [ 1 3 ]
D 2 7
P E G _ TX [ 1 4 ]
E 2 6
P E G _ TX [ 1 5 ]
D 2 5
e D P _ A U X
C 1 5
e D P _ A U X #
D 1 5
e D P _ T X [ 0 ]
C 1 7
e D P _ T X [ 1 ]
F 1 6
e D P _ T X [ 2 ]
C 1 6
e D P _ T X [ 3 ]
G1 5
e D P _ T X # [ 0]
C 1 8
e D P _ T X # [ 1]
E 1 6
e D P _ T X # [ 2]
D 1 6
e D P _ T X # [ 3]
F 1 5
e D P _ C OM P I O
A 1 8
e D P _ H P D #
B 1 6 e D P _ I C OM P O
A 1 7
R 1 2 2 *1 0 m i l_ 0 4
U 1 1
* W 8 3L 7 7 1 A W G
V D D
1
D +
2
D -
3
TH E R M
4
G N D
5
A L E R T
6
S D A T A
7
S C L K
8
Q1 8
* 2N 3 9 04
B
E
C
S M C _ C P U _ T H E R M [ 1 4 , 2 7 ]
3. 3 V
C R I T _ T E MP _ R E P # [ 1 8 ]
S M D _ C P U _ T H E R M [ 1 4 , 2 7 ]
C 9 7
*0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
TS # _ D I MM 0_ 1 [ 9 , 1 0 ]
D +_ C P U
D -_C P U
Analog Thermal Sensor
On Board CPU Thermal Sensor
C 5 4 0 *0 . 1 u _1 0 V _ X 7R _ 04
C 10 0
0 . 1 u _1 0 V _ X 7R _ 04
E D P _ C OM P
R 3 89
1 K _ 0 4
1 . 05 V S _ V T T
E D P _ H P D #
P Q 4 7
* MT N 7 0 0 2 Z H S 3
G
D
S
EDP Function Disable
EDP_HPD: Pull-up10K- DISABLED
E MB _ H P D [ 1 1]
R 3 8 8
*1 0 0 K _ 04
Q1 7
*T MP 2 0
N C
1
GN D
2
V O
3
G N D
5
V C C
4
SC70-5 & SC70-3 Co-lay
PLACE NEAR U3
1
3
2
R 3 9 0
24 . 9 _ 1 %_ 0 4
R 6 3 2 4 . 9_ 1 % _ 04
D MI _ R XP 1 [ 15 ]
D MI _ R XP 0 [ 15 ]
1 . 0 5V S _ V TT
1 . 0 5V S _V TT
D MI _ R XN 1 [ 15 ]
D MI _ R XP 3 [ 15 ]
D MI _ R XP 2 [ 15 ]
D MI _ R XN 2 [ 15 ]
D MI _ R XN 3 [ 15 ]
D MI _ R XN 0 [ 15 ]
D MI _ T X P 0 [ 15 ]
3. 3 V [ 3 , 8 , 11 , 1 3 , 1 4, 15 , 1 7 , 1 8, 1 9 , 2 0 , 22 , 2 3 , 2 6 , 28 , 3 0 , 3 1, 3 3 , 3 4 , 3 5]
1 . 05 V S _V T T [ 3 , 5, 18 , 1 9 , 2 0, 3 4 , 3 6 ]
F D I _T X N 2 [ 1 5 ]
F D I _T X N 0 [ 1 5 ]
F D I _T X N 5 [ 1 5 ]
F D I _T X N 1 [ 1 5 ]
F D I _T X N 7 [ 1 5 ]
F D I _T X N 4 [ 1 5 ]
F D I _T X N 3 [ 1 5 ]
F D I _T X P 5 [ 1 5 ]
F D I _T X P 1 [ 1 5 ]
F D I _T X N 6 [ 1 5 ]
F D I _T X P 3 [ 1 5 ]
F D I _T X P 2 [ 1 5 ]
F D I _T X P 0 [ 1 5 ]
F D I _T X P 6 [ 1 5 ]
F D I _T X P 7 [ 1 5 ]
F D I _T X P 4 [ 1 5 ]
F D I _ L S Y N C 0 [ 1 5 ]
F D I _ L S Y N C 1 [ 1 5 ]
F D I _I N T [ 1 5 ]
Sandy Bridge Processor 1/7
( DMI,PEG,FDI )
F D I _ F S Y N C 1 [ 1 5 ]
F D I _ F S Y N C 0 [ 1 5 ]
D MI _ T X P 3 [ 15 ]
D MI _ T X P 2 [ 15 ]
D MI _ T X P 1 [ 15 ]
DP Compensation Signal
D MI _ T X N 1 [ 15 ]
P E G_ C OM P
20 mil
D MI _ T X N 0 [ 15 ]
D MI _ T X N 2 [ 15 ]
D MI _ T X N 3 [ 15 ]
Q1 6
G 71 1 S T 9 U
O U T
1
V C C
2
G N D
3
1: 2 (4 mi ls :8 mi ls )
3 . 3 V
T H E R M _ V OL T [ 2 7 ]
C 5 4 1 *0 . 1 u _1 0 V _ X 7R _ 04
9/20
EVT
D P _ T X N 3 [ 1 1]
C 9 9
0 . 1 u_ 1 0 V _ X7 R _0 4
CAD NOTE: DP_COMPIO and ICOMPO signals
should be shorted near balls and routed with
- typical impedance < 25 mohms