Clevo P775TM, Service Manual

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Schematic Diagrams
P PS8330B B - 37
B.Schematic Diagrams
P PS8330B
Sheet 36 of 69
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
check IN_CA,1/13
DESIGN NOTE:CFG0
Configuration pin for automatic EQ and
Aux interception; Internal pull down at
150Kohm,3.3V I/O
L: default, automatic EQ enable and Aux interception enable
H: automatic EQ disable and AUX interception enable
M: automatic EQ disable and AUX interception
disable,no pre-emphasis, 600mVpp swing
DESIGN NOTE:CFG1
Configuration pin for auto test and input offset
cancellation,3.3V IO, internal pull up at 150K
H: default, auto test disable and input offset cancellation
enable
L: auto test enable and input offset cancellation enable
M: auto test disable and input offset cancellation disable
DESIGN NOTE:PEQ
Programmalbe input equalization levels;internal pull
down at 150k ,3.3v I/O
L: default, LEQ, compensate channel loss up to 12dB at
HBR2
H: HEQ, compensate channel loss up to 15dB at HBR2
M:LLEQ, compensate channel loss up to 5dB at HBR2
DEFAULT:LOW
$XWRWHVWHQDEOH,QWHUQDOSXOOGRZQDWa. 㫉
, 3.3V I/O.
L: Auto test disable & input offset cancellation enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
$XWRPDWLF(4GLVDEOH,QWHUQDOSXOOGRZQDWa. 㫉
, 3.3V IO
L: Automatic EQ enable (default)
H: Automatic EQ disable
Programmable input equalization levels; Internal pull down at
~150K
㫉
, 3.3V I/O.
L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
Port switching control or priority configuration;
Internal pull down at ~150K
㫉
, 3.3V I/O.
L: Port1 is selected or with higher priority (default)
H: Port2 is selected or with higher priority
Chip operational mode configuration;
Internal pull down at ~150K
㫉
, 3.3V I/O.
L: Control switching mode (default)
H: Automatic switching mode
3 Levels Input:
L: Low
H: High
M: VDD33/2, connect both
pull-up and pull-down resistors
AUX interception disable for Port y (y = 1, 2). Internal pull down at ~150K
㫉
,
9,2
L: AUX interception enable, driver configuration is set by link training (default)
H: AUX interception disable, driver output with fixed 800mV and 0dB
M: AUX interception disable, driver output with fixed 400mV and 0dB
Hybrid DDC/AUX
Output swing adjustment for Port y (y = 1, 2). Internal pull down at ~150K
㫉
,
9,2
L: default
H: +20%
M: -16.7%
PD PIN: 8330
HI ->DEFAULT
LOW->CHIP PWR DOWN
PD PIN: 8330
HI ->DEFAULT
LOW->CHIP PWR DOWN
PD PIN: 8338
L:default
H:Chip power down
PD PIN: 8338
L:(default)
H:Chip power down
CAD_SNK
PS8330B_CFG1
PS8330B_CFG0
PEQ
HPD_SRC
CAD_SRC
IN_DDC_SDA IN_DDC_SCL
PS8330B_AUXp PS8330B_AUXn
OUT2_AUXp_SCL
OUT2_AUXn_SDA
PS8330B_AUXn
PS8330B_AUXp
IN_DDC_SDA
IN_DDC_SCL
IN_DDC_SCL
CAD_SRC
IN_AUXn
IN_DDC_SDA
IN_DDC_SCL
DP_A1
DP_A#3
PS8330B_IN_D2n
IN_D2p
PI1
PI0 PSCFG0 PC11 PC20 PC21 PC10
PSPEQ
3.3VS
IN_D1p
PSPEQ
3.3VS
IN_CA_DET
PI0
PS8330B_IN_D3p
IN_D2n
DP_A#1
PS8330B_IN_D3n
IN_D3p
DP_A#2
IN_D3n
CAD_SRC
DP_A3
PI1
PSCFG0
DP_A2
PS8338B_SW
MUX_AUXP_DDC_SCL MUX_AUXN_DDC_SDA
IN_AUXp IN_AUXn
PC10
IN_AUXp
IN_CA_DET
GND
MUX_AUXP_DDC_SCL
MUX_AUXN_DDC_SDA
PC21
PC20
DP_A_HPD
PS8330B_IN_D0p
IN_D0p
PS8330B_IN_D0n
PS8330B_IN_D1p
IN_D0n
PS8330B_IN_D1n
DP_A0
PS8330B_IN_D2p
IN_D1n
DP_A#0
IN_DDC_SDA
PS8330B_IN_D0p
PS8330B_IN_D0n
IN0P_R
IN0N_R
PS8330B_IN_D1n
PS8330B_IN_D1p IN1P_R
IN1N_R
PS8330B_IN_D2n
PS8330B_IN_D2p IN2P_R
IN2N_R
PS8330B_IN_D3n
PS8330B_IN_D3p IN3P_R
IN3N_R
HPD_SRC_R HPD_SRC
OUT2_HPD
PC11
PS8330B_PCH
8338PD
PS8338B_PD
PS8330B_CFG1
PS8330B_CFG0
PEQ
8338PD
PS8338B_PD
3.3VS 3.3VS
3.3VS
3.3VS
3.3VS 3.3VS 3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
NV3V3 NV3V3 NV3V3
3.3VS
3.3VS
3.3VS
3.3VS
OUT2_D0p 37
OUT2_D0n 37
OUT2_D1p 37
OUT2_D1n 37
OUT2_D2n 37
OUT2_D2p 37
OUT2_D3p 37
OUT2_D3n 37
DP_A0 12
DP_A#0 12
DP_A1 12
DP_A#1 12
DP_A2 12
DP_A#2 12
DP_A3 12
DP_A#3 12
DP_A_HPD 12
OUT2_AUXp_SCL 37
OUT2_AUXn_SDA 37
G_DPA_MODE 12
OUT2_HPD 37
OUT1_AUXp_SCL 12
OUT1_AUXn_SDA 12
MUX_0P 15
MUX_HPD 15
MUX_2P 15
MUX_1N 15
MUX_1P 15
MUX_0N 15
MUX_3N 15
MUX_3P 15
MUX_2N 15
MUX_AUXN_DDC_SDA 15
MUX_AUXP_DDC_SCL 15
3.3VS 7,8,9,10,11,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,38,41,42,43,44,46,47,49,51
PS8338B_SW 17
NV3V3 11,12,13,14,47
PS8330B_PCH 16
Title
Size Document Number R e v
Date: Sheet o f
6-71-P77F0-D02
2.0
[36] AR_PS8330B
A3
36 69 Monday, August 28, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number R e v
Date: Sheet o f
6-71-P77F0-D02
2.0
[36] AR_PS8330B
A3
36 69 Monday, August 28, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number R e v
Date: Sheet o f
6-71-P77F0-D02
2.0
[36] AR_PS8330B
A3
36 69 Monday, August 28, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
R350 100K_04
C83
0.01u_16V_X7R_04
R68 *4.7K_04
R73 *4.7K_04
R529
4.7K_04
R537 *4.7K_04
R880 *0_04
Q53
2SK3018S3
G
D
S
R63 *4.7K_04
C82 0.1u_10V_X7R_04
R542
4.99K_1%_04
R540
100K_04
C71 0.1u_10V_X7R_04
C72 0.1u_10V_X7R_04
C75 0.1u_10V_X7R_04
C68 0.1u_10V_X7R_04
R69 *4.7K_04
R539 *4.7K_04
PS8330B
U26
PS8330B
VDD3
3
1
CEXT
2
I2
C_
ADDR
3
SCL
_
C
TL
PEQ
4
SDA_
CL
TCFG
0
5
VDD3
3
6
REXT
7
CAD_
SRC
8
HPD_
SRC
9
CAD_
SNK
10
HPD_
SNK
11
VDD3
3
12
OUT3n
13
OUT3p
14
NC
15
OUT2n
16
OOUT2p
17
GND
18
OUT1n
19
OUT1p
20
NC
21
OUT0n
22
OUT0p
23
GND
24
VDD3
3
36
RST
#
35
SDA_
DDC
34
SCL
_
DDC
33
VDD3
3
32
GND
31
AUX_
SRCp
30
AUX_
SRCn
29
AUX_
SNKp
28
AUX_
SNKn
27
PD#
26
VDD3
3
25
IN3n
48
IN3p
47
NC
46
IN2n
45
IN2p
44
NC
43
IN1n
42
IN1p
41
CFG1
40
IN0n
39
IN0p
38
NC
37
EPAD
49
Q43
AO3415
G
D
S
C336
0.1u_10V_X7R_04
C361
2.2u_6.3V_X5R_04
C569 0.1u_10V_X7R_04
Q44
AO3415
G
D
S
R544
4.7K_04
C66
2.2u_6.3V_X5R_04
R366
10K_04
R925
*100K_04
R368 *4.7K_04
C74 0.1u_10V_X7R_04
C576 0.1u_10V_X7R_04
R543
100K_04
C73 0.1u_10V_X7R_04
R567
100K_04
R924
*10K_04
R72 *4.7K_04
R351 100K_04
R384 *4.7K_04
C572 0.1u_10V_X7R_04
C556 0.1u_10V_X7R_04
R530
4.7K_04
R565 *0_04
R352
1M_04
R62 *4.7K_04
C86
0.01u_16V_X7R_04
R528 *4.7K_04
R74 *4.7K_04
R370 *4.7K_04
C575 0.1u_10V_X7R_04
C909
*0.1u_16V_Y5V_04
Q51
AO3415
G
D
S
C70 0.1u_10V_X7R_04
R367 *4.7K_04
R527 *4.7K_04
C573 0.1u_10V_X7R_04
R566 0_04
Q52
AO3415
G
D
S
R383 *4.7K_04
C87
0.1u_16V_X7R_04
R538 *4.7K_04
Q65
*2SK3018S3
G
D
S
C570 0.1u_10V_X7R_04
R353
4.99K_1%_04
R71 *4.7K_04
R546
4.7K_04
R923 *0_04
C360
0.01u_16V_X7R_04
Q7
2SK3018S3
G
D
S
R369 *4.7K_04
C574 0.1u_10V_X7R_04
R75
*4.7K_04
U7
PS8338B
PI1/SCL_CTL
1
I2C_CTL_EN
2
IN_HPD
3
IN_CA_DET
4
VDD33
5
IN_D0p
6
IN_D0n
7
PEQ
8
IN_D1p
9
IN_D1n
10
GND
11
IN_D2p
12
IN_D2n
13
PD
14
IN_D3p
15
IN_D3n
16
CEXT
17
SW
18
GND
19
REXT
20
VDD3
3
21
IN_
DDC_
SCL
22
IN_
DDC_
SDA
23
IN_
A
UXp
24
IN_
A
UXn
25
O
U
T
1_A
U
X
p_S
C
L
26
O
U
T
1_A
U
X
n_S
D
A
27
O
U
T
2_A
U
X
p_S
C
L
28
O
U
T
2_A
U
X
n_S
D
A
29
VDD3
3
30
OUT2_D3n
31
OUT2_D3p
32
OUT2_CA_DET
33
OUT2_D2n
34
OUT2_D2p
35
OUT2_D1n
36
OUT2_D1p
37
OUT2_HPD
38
OUT2_D0n
39
OUT2_D0p
40
OUT1_D3n
41
OUT1_D3p
42
OUT1_CA_DET
43
OUT1_D2n
44
OUT1_D2p
45
OUT1_D1n
46
OUT1_D1p
47
OUT1_HPD
48
OUT1_D0n
49
OUT1_D0p
50
VDD3
3
51
GND
52
PC2
1
53
PC2
0
54
PC1
1
55
PC1
0
56
VDD3
3
57
CF
G1
58
CF
G0
59
PI0
/SDA_
CTL
60
EPAD
61
R541
100K_04
C65
0.1u_10V_X7R_04
R70
*4.7K_04
C359
2.2u_6.3V_X5R_04
R531
4.7K_04
C571 0.1u_10V_X7R_04
R545
4.7K_04
C67 0.1u_10V_X7R_04
C567 0.1u_10V_X7R_04
C69 0.1u_10V_X7R_04
C81 0.1u_10V_X7R_04