Clevo NP50DB, Service Manual

Page: 51 / 106

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG7
DEFENSIVE PULL DOWN SITE
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG4
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
DISPLAY PORT PRESENCE STRAP
CFG2
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
CFG[0]: Stall reset sequence after PCU PLL
Ʉ
lock until de-asserted:
— 1 = (Default) Normal Operation; No
stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
Ʉ
CFG[2]: PCI Express* Static x16 Lane Ʉ
Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane. Ʉ
CFG[4]: eDP enable:
Ʉ
— 1 = Disabled.
— 0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation
Ʉ
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training: Ʉ
— 1 = (default) PEG Train immediately
following RESET# de assertion.
— 0 = PEG Wait for BIOS for training.
CFG[19:8]: Reserved configuration lanes. Ʉ
TO EC
NEAR CPU
TO PCH-H
VCCST_PWRGD
CAD Note: Capacitor need to be placed
close to buffer output pin
Configuration Signals: The CFG signals have a
default value of '1' if not terminated on the board.
Refer to the appropriate platform design guide for
pull-down recommendations when a logic low is
desired.
Rubband
2019/12/17
VIDALERT#
PROCHOT#
H_PROCHOT#
VCCST_PW RGD_CPU VCCST_PW RGD
PM_DOW N
PECI
H_SKTOCC_N
H_TDO
H_TDI
H_TMS
H_TCK
H_TRST#
H_PREQ#
H_PRDY#
CFG_RCOMP
CFG0
CFG3
CFG4
CFG7
H_TDO
H_TCK
H_SKTOCC_N
CFG8
SYS_PW RGD#
VCCST_PW RGD
H_PROCHOT#
CFG_1
CFG9
CFG11
CFG14
CFG15
H_TDI
H_TMS
1.05DX_VCCSTG
3.3VA
1.05V_VCCST
1.05V_VCCST
VDD3
1.05DX_VCCSTG
H_PROCHOT# 46
PCH_CPU_BCLK_R_DN 29
PCH_CPU_BCLK_R_DP 29
PCH_CPU_PCIBCLK_R_DN 29
PCH_CPU_PCIBCLK_R_DP 29
CPU_24MHZ_R_DN 29
CPU_24MHZ_R_DP 29
H_PW RGD 27
PLTRST_CPU_N 26
H_PM_SYNC 26
H_SKTOCC_N 28,32
DDR_VTT_PG_CTRL 44
H_CPU_SVIDCLK 46
H_CPU_SVIDDAT 46
H_CPU_SVIDALRT# 46
PCH_THERMTRIP# 26
PCH_PECI 26
H_PM_DOW N 26
H_PECI 39
ALL_SYS_PW RGD 22,25,39,46
H_PROCHOT_EC 39
H_TCK 27
H_TMS 27
H_TDO 27
H_TDI 27
H_TRST# 32
H_PREQ# 32
H_PRDY# 32
VDD3 24,25,27,30,32,33,34,36,38,39,40,41,42,43,46,47,49,50,51,52,53,54,55
1.05V_VCCST 6,26,42,46
3.3VA 24,25,26,27,30,32,38,42,47
1.05DX_VCCSTG 6,47
Title
Size Document Number R e v
Date: Sheet o f
6-71-NP500-D02
D02
[04]Processor 3/6-CLK/JTAG/MISC
A3
4 59 Monday, February 24, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N18P
Title
Size Document Number R e v
Date: Sheet o f
6-71-NP500-D02
D02
[04]Processor 3/6-CLK/JTAG/MISC
A3
4 59 Monday, February 24, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N18P
Title
Size Document Number R e v
Date: Sheet o f
6-71-NP500-D02
D02
[04]Processor 3/6-CLK/JTAG/MISC
A3
4 59 Monday, February 24, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N18P
R322 *12.1_1%_04
CPU
T2
CPU
R346 *1K_04
CPU
R332 499_1%_04
CPU
R33
56.2_1%_04
CPU
R343 1K_04
CPU
C617
47p_25V_NPO_02
CPU
T58
CPU
5 OF 13
U16E
CML_H_IP_EXT/BGA
CPU
VIDSOUT
BH29
DDR_VTT_CNTL
BT13
VCCST_PWRGD
H13
PM_SYNC
BM34
PM_DOWN
BP31
PECI
BT34
CFG_18
BN22
PROC_TCK
BR28
CFG_19
BP22
THERMTRIP#
J31
PROC_TDO
BT28
CFG_0
BN25
PROC_TRST#
BP30
CFG_1
BN27
PROC_SELECT#
BN1
ZVM#
AT13
SKTOCC#
BR33
CFG_2
BN26
CFG_RCOMP
BT25
CFG_3
BN28
PROC_PREQ#
BL30
CFG_4
BR20
CFG_10
BT23
RESET#
BP35
CFG_5
BM20
CLK24N
D31
PROCPWRGD
BT31
CFG_11
BT22
CFG_6
BT20
BPM#_0
BR27
VIDSCK
BH32
BCLKN
A32
PCI_BCLKN
C36
BPM#_1
BT27
CFG_7
BP20
CFG_12
BM19
CLK24P
E31
CFG_8
BR23
CFG_13
BR19
BPM#_2
BM31
BCLKP
B31
PCI_BCLKP
D35
BPM#_3
BT30
PROCHOT#
BR30
CFG_9
BR22
CFG_14
BP19
RSVD2
AY13
CFG_15
BT19
RSVD1
AU13
PROC_PRDY#
BP27
CFG_16
BP23
CATERR#
BM30
PROC_TDI
BL32
MSM#
AW13
PROC_TMS
BP28
CFG_17
BN23
VIDALERT#
BH31
S
D
G
Q29B
MTDK3S6R
CPU
5
3
4
T61
CPU
R348
100K_04
CPU
C613
*0.1u_10V_X7R_04
CPU
R48 *1K_04
CPU
T62
CPU
R323
1K_04
CPU
C167
*0.1u_10V_X7R_04
CPU
T57
CPU
R325 *0402_short
CPU
R326 60.4_1%_04
CPU
R681 10K_04 CPU
C609
*0.1u_10V_X7R_04
CPU
R35
220_04
CPU
S
D
G
Q29A
MTDK3S6R
CPU
2
6
1
R336 0_04
CPU
Q32
2SK3018S3
CPU
G
D
S
R319 20_1%_04
CPU
R333 100_04
CPU
R43
49.9_1%_04
CPU
R324
100K_04
CPU
T4
CPU
R341 51_04
CPU
R349 *1K_04
CPU
R347 51_04
CPU
R37 51_04
CPU
R34
100_04
CPU
T3
CPU
T7
CPU
R354 1K_04 CPU
R329 100K_04
CPU
Sheet 4 of 59
Processor 3/6
Schematic Diagrams
Processor 3/6 B - 5
B.Schematic Diagrams
Processor 3/6