Schematic Diagrams
VT8237A-2 B - 17
B.Schematic Diagrams
VT8237A-2
Sheet 16 of 40
VT8237A-2
I D E _ P D D 0
S A T A T XP 0
I N T _ I R Q 15
P M_ S T P C P U #
3 . 3 V S
3 . 3 V
8 23 7 _S U S B #
GP O1
R 3 48
10 K _ 0 6
GP I O D
R 32 3
1 K _ 06
3. 3 V
I D E _ P D C S 3 #
GP O 04
1:Vlink Compensation(Manual setting)
S U S B # 1 3, 15 , 2 0, 2 3 , 27 , 2 8 , 34
S M I # 23
I D E _ S D D 0
S U S A #
1:VKCOMP for Vlink at 4X mode 0.9V
I D E _P D A 0
T P O
I D E _ S D D 8
S U S A #
I D E _ P D D 7
C 37 3
1 U _ 10 V _ 06
R 2 86
0_ 0 6
R 3 1 6
0 _0 6
I D E _S I OR D Y
P E X ME S C I #
S U S C # 2 3
S A T A 5 0 C OM P
F B 13
H C B 2 0 12 K F -1 2 1T 3 0_ 0 8
A Z _B I T C L K 2 7
I D E _ S I OR D Y
F B 21
H C B 2 0 12 K F -1 2 1T 3 0_ 0 8
R 2 76
0_ 0 6
I D E _ P D D 13
C L K R U N #
R 36 1
* 0_ 0 4
R 60 3
0 _ 06
C 4 9 3 2 2P _ 5 0 V _0 6
GPIO C,A 1,1:Auto Mode
3 . 3 V S
I D E _S D D R E Q
VT8237R plus => 4.7K
VT8237A => 6.12K
AP339A
I D E _S D C S 1 #
A Z _ S D I N 0
I D E _ S D D 3
A Z _ S D I N 1
I D E _ P D D 8
R 5 65
4 . 7 K _ 06
R 6 56
1 0 K _ 06
3 . 3V S
I D E _ I R Q
1 8
I D E _P D A 1
R 36 0
0 _ 04
G P O0 4 15
V D D A 0
I D E _ P D A 0
I D E _S D I OR #
R 5 44
1 0 K _ 06
WA KE ON L AN
C9 60 525
R 5 54
4 . 7 K _ 06
R 35 1
0 _ 06
U 35
7 4 A H C 1 G0 8 GW
2
1
4
3
5
R 6 20
4 . 7 K _ 06
3 . 3V S
GP I O C
A Z _ S D I N 1
C P U MI S S
A Z _ S D O U T
F B 1 4
H C B 32 1 6K F -8 0 0 T3 0 _1 2
0:V4-lite support(Disable)
A Z _ S Y N C
A C _ S P K R
GP I 04
I D E _ S D D 9
R 2 69
0_ 0 6
R 6 29
1 M _0 6
V C C R T C
S MB _ S B D A T A
I D E _ S D D R E Q
A Z _R S T# 2 7
S E R I R Q
S D I N 3
C 7 08
* 10 U _ 1 0V _ 0 8
Z 1 6 1 0
Z 1 6 15
R 62 3
1 K _ 06
Z 1 6 13
I D E _ S D D 11
I D E _ P D D 12
+
C 3 8 9
47 0 U _ 4 V _D
S C I # 23
S D I N 2
I D E _ P D D 7
2 5M H Z X I _S
R N 29
1 K _ 8P 4 R _ 0 6
1
2
3
4
5
6
7
8
GPIO D 0:AGTL+ pullup Enable
I D E _ P D A 2
3. 3 V
S A TA T X P 0
1 8
R 6 24
4 . 7 K _ 06
R 58 6
* 2. 2 K _ 06
R 3 1 1
0 _0 6
P M _ S TP P C I # 2
W A K E
P M_ S T P P C I #
A Z _ S D OU T
S M B _ S B D A T A 2 , 9, 1 0 , 11
W A K E
I D E _ P D D 15
C 4 56
1 5 P _ 50 V _ 06
R 5 35
4 . 7 K _ 06
2 . 5V S
V D D A 0
I D E _ P D D 6
C L K R U N #
R 35 3
* 0_ 0 6
S E R I R Q 19 , 2 3
I D E _S D A 1
GP O 1
R 6 28
1 M _0 6
GPIO B 0:IOQ Depth 8 Level
P E XM E S C I # 7
P M_ B A T LO W #
0/1:Enable/disable Auto Reboot
A Z _S D I N 1 27
I D E _ P D D 10
I N T _ I R Q
R 35 0
2 . 2 K _0 6
R 5 74
4 . 7 K _ 06
R 35 5
* 0_ 0 6
C P U MI S S
R 36 2
1 K _ 06
R 5 81
1 0 K _ 06
8 23 7 _P W R OK
8 2 37 _ P W R O K
I D E _ S D D 15
R 8 6 8
0 _0 6
R 2 62
1 0 K _ 06
R 36 3
* 2. 2 K _ 06
W A K E 7
S B _ P W R OK
P M_ B A T LO W #
A Z _ R S T #
I D E _ P D D 4
R 5 98
4 . 7 K _ 06
S MI #
I D E _ P D D 9
R 32 4
* 2. 2 K _ 06
R 3 08
6 . 1 9 K _1 % _0 6
C 43 4
1 U _ 1 0V _ 0 6
3 . 3V S
2 . 5V
I D E _ P D D 2
R 5 75
4 . 7 K _ 06
0/1:Enable/disable100Mhz VLink clock(Reserved)
S U S B #
A C _ S P K R
S E E D I
1 7
P ME #
T P O
2 . 5V S
3 . 3 V S
I D E _ P D D R E Q
1 8
3 . 3 V S
I D E _ S D D 2
GP I 0
S B _ P W R OK
A Z _ B I TC LK
I D E _S D A 2
R 61 8
2 2 _0 6
R 6 31
4 . 7 K _ 06
I D E _ P I OR D Y
1 8
Z 1 6 17
S I D E V R E F
R 3 66
4 . 7 K _ 06
Z 1 6 04
R 35 7
* 1K _ 0 6
I D E _ P D A 1
S U S C #
I N T_ I R Q
2. 5 V S A T A
0\1:P4/V4 Bus \ C3 Bus
GP I 0
I D E _S D A 0
I D E _P D I OR #
GP I O C
G P O0 1 1
GP I O A
R 5 97
4 . 7 K _ 06
R 8 6 9
*0 _ 06
I D E _P D C S 1 #
S A TA T X N 0
1 8
2 5 MH Z XI _ S
Z 1 6 0 7
C960531
I D E _P D D [ 0 . . 1 5]
1 8
G P O1 2 7
R I N G
I D E _ S D D 1
C 4 8 7 2 2P _ 5 0 V _0 6
P M _C LK R U N #
8 23 7 T E S T
I D E _ P D D 5
P M_ S U S _ S T A T#
R 59 5
2 2 _0 6
I D E _P D D A C K #
GP I O D
S MB _ A L E R T #
B GA 6 B
V T8 2 37 A -B G A 54 1
A A 2 2
Y 2 4
A A 2 6
A A 2 5
A B 2 6
A C 2 6
A C 2 3
A D 2 5
A D 2 6
A C 2 4
A C 2 5
A B 2 4
A B 2 3
A A 2 4
Y 2 6
A A 2 3
W 2 3
V 2 5
W 2 4
Y 2 3
V 2 4
W 2 6
Y 2 5
Y 2 2
V 2 2
V 2 3
T 1
U 3
V 2
U 1
V 3
T 2
U 2
T 3
A D 2 4
A E 2 6
A C 2 0
A B 2 0
A C 2 1
A E 1 8
A F 1 8
A D 1 8
A D 1 9
A F 1 9
A E 2 0
A F 2 0
A D 2 0
A E 2 1
A F 2 1
A D 2 1
A D 2 2
A F 2 2
A D 1 7
A D 2 3
A F 2 3
A E 2 3
A F 1 7
A F 2 5
A F 2 6
A F 2 4
A C 2 2
A E 2 4
A D 2
Y 2
A A 1
W 4
A C 1
V 4
Y 3
A B 3
A A 2
A D 3
A F 2
A B 1
A C 4
A B 2
A C 2
A A 3
A E 2
A E 5
A F 5
A C 6
A D 5
A B 7
A C 7
A D 6
AA
4
AB
4
AB
5
AB
6
J9 J1
0
J1
1
AF
1
4
L1
3
L14
A E 9
A F 1
L1
5
K9
L9
J1
2
L1
8
M9
AB1
4
AC
14
AD
1
2
AD
1
3
AD
1
4
AD
1
5
AD
16
AE1
2
AE1
4
AE1
6
AF
1
2
L1
6
M1
1
A C 1 1
A C 1 7
A B 1 3
A C 1 3
A E 1 5
A F 1 5
A B 1 5
A C 1 5
AF
16
L11
L1
2
T4 U4
A D 9
A F 8
A B 8
A C 3
A D 1
A E 1
Y 4
A F 9
Y 1
A E 3
A E 1 3
A F 1 3
A C 1 0
A B 1 0
A E 1 1
A F 1 1
A D 1 1
A E 1 0
A F 1 0
A C 1 9
A B 2 1
A B 1 1
A B 1 7
W 1 2
W 1 3
W 1 4
W 1 5
W 1 6
M1
8
N9
N1
8
P9
P1
8
R9 R1
8
T9 T1
8
U9 U1
8
V9
V1
0
V1
1
V1
2
V1
3
V1
4
V1
5
V1
6
V1
7
V1
8
AC
16
AC
1
2
AB1
6
AB1
2
M1
2
M1
3
M1
4
M1
5
M1 6
N 1 1
N 1 2
N 1 3
N 1 4
N 1 5
N 1 6
F6 F7
J5 K5 P5
R5
W 5
V 5
K1
8
Y 5
P D D 0 0
P D D 0 1
P D D 0 2
P D D 0 3
P D D 0 4
P D D 0 5
P D D 0 6
P D D 0 7
P D D 0 8
P D D 0 9
P D D 1 0
P D D 1 1
P D D 1 2
P D D 1 3
P D D 1 4
P D D 1 5
P D A 0 / P D A 0 *
P D A 1 / P D A 1 *
P D A 2 / P D A 2 *
P D D R Q
P D D A C K / P D D A C K *, P D D A C K
P D I OR / P H D MA R D Y / P H S TR OB E
P D I OW / P S TO P
P D R D Y / P D D MA R D Y / P D S T R OB E
P D C S 1 / P D C S 1 *, P D C S 1
P D C S 3 / P D C S 3 *
A C B I T C L K , A Z B I T C L K
A C S D I N 0, A Z S D I N 0
A C S D I N 1, A Z S D I N 1
A C S D I N 2 , A Z S D I N 2 / GP I 2 0 / GP O2 0 / P C S 0
A C S D I N 3, A Z S D I N 3 / GP I 2 1 / GP O2 1 / P C S 1 / S L P B T N
A C S Y N C , A Z S Y N C / A C S Y N C *
A C S D OU T, A Z S D OU T/ A C S D O U T *
A C R S T , A Z R S T
I R Q1 4
I R Q1 5
S D D 0 0
S D D 0 1
S D D 0 2
S D D 0 3
S D D 0 4
S D D 0 5
S D D 0 6
S D D 0 7
S D D 0 8
S D D 0 9
S D D 1 0
S D D 1 1
S D D 1 2
S D D 1 3
S D D 1 4
S D D 1 5
S D D R Q
S D D A C K
S D I OR / S H D MA R D Y / S H S TR OB E
S D I OW / S S TO P
S D R D Y / S D D MA R D Y / S D S T R OB E
S D C S 1
S D C S 3
S D A 0
S D A 1
S D A 2
P W R B T N
R I N G/ GP I 03
E X T S MI / GP I 02
P ME
L I D / GP I 04
B A T L OW / GP I 05
S U S S T 1 / GP O 03
S U S C L K / GP O 04
S U S A / GP O 02
S U S B
S U S C
S MB A L R T
S M B C K 1
S MB D T1
G P I 01 , G P I 01 / T H R M T R I P
GP O 00
GP I 00
S t rap _ V D 1 *, G P I OA */ P C R E Q A *
S t rap _ V D 0 *, G P I OC * / P C GN T A *
S t rap _ V D 3 *, G P I OD * / P C GN T B *
S t rap _ V D 2 *, G P I OB */ P C R E Q B *
P C K R U N
C P U S T P / GP O 05
P C I S T P / P C I S TP * / GP O 06
V
S
U
S
33-
1
VS
U
S
33
-2
VS
U
S
3
3-
3
V
S
U
S
33-
4
VC
C
25
-1
VC
C
2
5-
2
V
C
C
25-
3
G
NDA
T
S
1
1
GN
D
GN
D
T E S T
P W R OK
GN
D
V
CC2
5
-5
VC
C
25
-6
VC
C
2
5-
4
VC
C
2
5-
7
V
C
C
25-
8
GN
D
A
T
S
0
G
NDA
T
S
1
GN
D
A
T
S
2
GN
D
A
T
S
3
GN
D
A
T
S
4
GN
D
A
T
S
5
G
NDA
T
S
6
GN
D
A
T
S
7
GN
D
A
T
S
8
GN
D
A
T
S
9
GN
D
A
T
S
1
0
GN
D
GN
D
V C C A S 2
V C C A S 1
S TX P 1
S TX N 1
S R X P 2
S R X N 2
S TX P 2
S TX N 2
GN
D
A
T
S
1
2
GN
D
GN
D
V
S
U
S
25-
1
VS
U
S
25
-2
S E R I R Q
S P K R / S P K R *
O S C
S M B C K 2 / GP I 2 7 / GP O 27
S MB D T2 / GP I 2 6 / GP O 26
I N T R U D E R / GP I 16
A OL GP I / T H R M/ GP I 18
T P O
C P U MI S S / GP I 17
GP O 01
S R X P 1
S R X N 1
V C C A O
G N D A O
V C C A 33 , N C
GN D A 33 , N C
S R E XT
S X O
S X I
S V R E F , N C
S C OM P P , N C
V C C A S 4
V C C A S 3
V D D A T S -1
V D D A T S -2
V D D A T S -3
V D D A T S -4
V D D A T S -5
VC
C
2
5-
9
V
C
C
25-
10
VC
C
25
-1
1
VC
C
2
5-
1
2
V
C
C
25-
13
VC
C
2
5-
1
4
V
C
C
25-
15
VC
C
25
-1
6
VC
C
2
5-
1
7
V
C
C
25-
18
VC
C
25
-1
9
V
C
C
25-
20
VC
C
25
-2
1
VC
C
2
5-
2
2
V
C
C
25-
23
VC
C
25
-2
4
V
C
C
25-
25
VC
C
25
-2
6
VC
C
2
5-
2
7
V
C
C
25-
28
VC
C
25
-2
9
GN
D
A
S
1
G
N
D
AS2
G
N
D
AS3
G
N
D
AS4
GN
D
GN
D
GN
D
GN
D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN D
GN D
GN
D
N C , W A K E
R 2 96
5 . 6 K _ 06
R 3 81
4 . 7 K _ 06
0/1:Enable/disable LPC FWH command
S M B _ S B C L K 2 , 9, 1 0 , 11
GP I O B
P M_ S T P P C I #
R 5 52
4 . 7 K _ 06
5 V S
P M _ C L K R U N # 23
I D E _S D D A C K #
C 69 5
. 1 U _ 5 0 V _0 6
S MB _ S B C L K
P M _S T P C P U #
S M B C K 2
Z 1 6 16
C 4 5 2
1 5P _ 5 0V _ 0 6
0/1:Disable/Enable LAN shadow EEPROM
S I O_ OS C 2
S A TA R X N 0
R 5 45
4 . 7 K _ 06
+
C 3 6 2
*3 30 U _ 6 . 3 V _D
C 45 7
4 . 7U _1 0 V _ 08
I D E _ P D C S 3#
1 8
I D E _ P D A 1
1 8
S E R I R Q
S I O_ OS C
R 6 22
4 . 7 K _ 06
X 3
2 5M H z
1
2
S W I # 2 3
I D E _P D I OW #
S M I #
I D E _P D A 2
S M B D T 2
C 4 8 8 2 2P _ 5 0 V _0 6
I D E _ P D I O R #
1 8
I D E _P I OR D Y
I D E _ S D D 13
Z 1 6 14
1: V 4 s u pp o rt
2 . 5 V S
V D D A 33
GP I 0 4
A Z _ S D I N 0
C 4 9 2 2 2P _ 5 0 V _0 6
I D E _ S D D 5
2 5 MH Z XO _S
0/1:Enable/disable CPU FREQ strapping
2. 5 V S
S D I N 3
S MB C K 2
GP I O A
2 5M H Z X O_ S
I D E _ P D D 1
R 3 64
4 . 7 K _ 06
R 5 8 3
1 00 _ 08
S D I N 2
R I N G
R 59 6
2 2 _0 6
3 . 3 V
A C _ S P K R 2 7
S M B _S B D A TA
S M_ I N T R U D E R #
I D E _ S D D 4
I D E _ P D D [ 0 . . 15 ]
Z 1 6 02
A Z _S D OU T 2 7
I D E _S D I OW #
2 . 5 V S
P M _ S U S _ S TA T # 7
R 6 01
4 . 7 K _ 06
0:MOBILE MODE
A Z _ S Y N C
R N 9
1 K _8 P 4 R _ 0 6
1
2
3
4
5
6
7
8
C 3 8 1
4 . 7 U _ 1 0V _ 0 8
A C S D O
8 23 7 TE S T
R N 28
2 . 2 K _8 P 4 R _ 0 6
1
2
3
4
5
6
7
8
C 4 9 0
4. 7 U _ 1 0V _ 0 8
I D E _ P D I O W #
1 8
A C S Y N C
GP O0
C 4 4 9
. 1 U _ 5 0 V _0 6
C 69 6
. 1 U _ 5 0 V _0 6
GP I O B
GP O 0
V D D A 3 3
I D E _P D C S 3 #
R 3 58
4 . 7 K _ 06
R 2 93
*0 _0 6
R 3 65
1 0 K _ 06
3 . 3V
A Z _S Y N C
27
I D E _ P D C S 1#
1 8
82 3 7 _S U S B #
Z 1 6 11
2. 5 V S
P M _ S TP C P U # 2
I D E _ P D D A C K #
1 8
I D E _ S D D 7
S A TA R X P 0
R 5 99
1 0 K _ 06
R 6 21
1 0 K _ 06
P M E # 19 , 2 3, 2 6
I D E _ P D A 2
1 8
I D E _ P D A 0
1 8
I D E _ P D D 14
R 35 4
* 1K _ 0 6
R 36 8
* 2. 2 K _ 06
1:DESKTOP MODE
3 . 3 V
Z 1 60 6
S A T A T XN 0
R N 2 0
2 . 2 K _ 8P 4 R _ 0 6
1
2
3
4
5
6
7
8
R 63 3
* 2. 2 K _ 06
R 34 7
0 _ 06
R S MR S T#
17 , 2 3
Z 1 6 12
P W R _ B TN # 2 3
3 . 3V S
I N T_ I R Q1 5
R 6 27
4 . 7 K _ 06
R 6 2 6
1 0K _ 0 6
2 . 5 V S
A Z _S D I N 0 27
A Z _ S D OU T
I D E _S D C S 3 #
I D E _ S D D 6
C 4 4 0
. 1 U _ 5 0 V _0 6
S A T A R X P 0
1 8
A Z _ R S T #
A Z _ S Y N C
+
C 8 0 5
10 0 U _ 6 . 3V _ B
1
2
R 6 04
4 . 7 K _ 06
VKCOMP for Vlink at 4X mode
S MB _ A L E R T #
GP I 0 4
Power Up Strapping for VT8237A
2 . 5 V S A T A
S R E X T
S M B _S B C LK
R 28 5
3 6 0_ 1 %_ 0 6
I D E _ S D D 14
Z 1 6 0 9
I D E _ S D D 12
R 6 00
4 . 7 K _ 06
R 6 19
4 . 7 K _ 06
R 2 64
4 . 7 K _ 06
I D E _ S D D 10
S B _ P W R O K 7
A Z _ S D I N 0
P W R _ B T N #
P M _C LK R U N #
M960807
S R E X T
C 4 46
1 U _ 1 0V _ 0 6
3 . 3 V S
I D E _ P D D 11
C 69 8
. 1 U _ 5 0V _ 0 6
R S M R S T #
1 7, 2 3
Z 1 60 5
Z 1 6 18
C 4 32
4. 7 U _ 1 0V _ 0 8
C 4 4 7
. 1 U _5 0 V _0 6
S A T A R X N 0
1 8
Z 1 6 03
I D E _ S D D 7
R 63 2
1 K _ 06
P E X ME S C I #
Z 1 6 0 8
C 44 3
. 1 U _ 5 0V _ 0 6
1 : V 4 -li t e s up p ort
Z 1 6 01
I D E _ P D D 3
U 34
7 4 A H C 1 G0 8 GW
2
1
4
3
5
R 6 25
1 0 K _ 06
0:V4 support(Disable)
3 . 3V
S M_ I N T R U D E R #
I D E _P D D R E Q
S MB D T2
LAN PHY RESET:
P M_ S U S _ S T A T #
Summary of Contents for M670SRU
Page 1: ......
Page 2: ......
Page 3: ...Preface I Preface Notebook Computer M670SRU M675SRU Service Manual...
Page 50: ...Part Lists A 10 A Part Lists...
Page 92: ...Schematic Diagrams B 42 FINGERPRINT BOARD B Schematic Diagrams...
Page 93: ...www s manuals com...