Schematic Diagrams
B - 12 DVO Chrontel CH7107A (71-L27T0-002)
B.Schematic Diagrams
DVO Chrontel CH7107A
Sheet 11 of 29
DVO Chrontel
CH7107A
Z1108
L39
FCM2012K-121T 0805
R314
140_1%
TZ1120
R326
330
+
CT45
10u/10V_1206
TZ1101
DVOC_HSYNC
7
+1.5V
5,7,13..15,22,28
+3V
L2-
12
+3V
Z1103
Z1104
Z1102
+
CT49
10u/10V_1206
CA204
0.1u_X7R
Z1112
Z1120
CA209
0.1u_X7R
TZ1106
TZ1110
CA206
0.1u_X7R
+3V
Z1109
MI2C_DATA
7
R299
330_R
C311
0.1u_R
U20
P2781_R
1
2
3
4
5
6
7
8
XIN/CLK
XOUT
FS0
LF
VSS
MODout
FS0
VDD
LCLK-
12
DVOC_BLANK#
7
TZ1122
+
CT48
10u/10V_1206
Z1129
TZ1124
RN54
8P4R*75
1
2
3
4
5
6
7
8
CA190
0.1u_X7R
U0-
12
R330
0_R
Z1105
L38
FCM2012K-121T 0805
DVOC_CLK#
7
TZ1113
TZ1116
Z1119
CA208
0.1u_X7R
DVOBC_CLKIN
7
MI2C_CLK
TZ1129
UCLK+
12
L3+
12
R308
10K
L1-
12
R324
0_R
R317
0
DVOC_D9
TZ1103
DVOC_D[0..11]
7
L37
FCM2012K-121T 0805
+3V
DVOC_D4
C221
10p_R
TZ1123
Z1131
TZ1105
CA186
0.1u_X7R
U0+
12
CA194
100p
+5V
4,12..14,16,17,19,21..29
+3V
R300
330_R
L36
FCM2012K-121T 0805
DVOC_D10
U19
CH7017A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
LPLL_VDD
LPLLCAP
LPLL_GND
LGND
LL2C
LL2C#
LVDD
LDC7
LDC7#
LGND
LDC6
LDC6#
LVDD
LDC5
LDC5#
LGND
LDC4
LDC4#
LVDD
LVDD
LDC3
LDC3#
LGND
LL1C
LL1C#
LVDD
LDC2
LDC2#
LGND
LDC1
LDC1#
LVDD
LDC0
LDC0#
LGND
VSWING
DAC_VDD
ISET
DAC_GND
DACB0
DACA0
DACB1
DACA1
DACB2
DACA2
DACB3
DACA3
DAC_GND
C/HSYNC
BCO/VSYNC
TVPLL_GND
XI/FIN
XO
TVPLL_VCC
TVPLL_VDD
GPIO4
GPIO5
RESET#
P-OUT
VDDV
VREF1
FLD/STL1
DE1
DVDD
V1
H1
DGND
D1[0]
D1[1]
D1[2]
D1[3]
D1[4]
D1[5]
XCLK1#
DGND
XCLK1
D1[6]
D1[7]
D1[8]
D1[9]
D1[10]
D1[11]
DVDD
DVDD
D2[0]
D2[1]
D2[2]
D2[3]
D2[4]
D2[5]
XCLK2#
DGND
XCLK2
D2[6]
D2[7]
D2[8]
D2[9]
D2[10]
D2[11]
DGND
H2
V2
DVDD
DE2
FLD/STL2
AS
SPD
SPC
HIN
VIN
VREF2
SDD
SDC
DD1
DC1
DD2
DC2
V5V
HOUT
VOUT
HPD
HPINT#
GPIO0
GPIO1
GPIO2
GPIO3
ENAVDD
ENABKL
R305
10K_R
R307
10K_R
R301
330_R
TZ1115
R306
10K_R
+3V
3..6,12..17,19..24,26..29
DVOC_VSYNC
7
Z1121
Y1
14.318MHz
1
2
L0+
12
+1.5V
TZ1131
TZ1102
TZ1111
R302
1K
CA187
0.1u_X7R
TZ1117
LCLK+
12
RN55
8P4R*75
1
2
3
4
5
6
7
8
U2-
12
DVOC_D2
Z1114
R316
0
L1+
12
+1.5V
TZ1125
TZ1118
R328
0_R
Z1113
Z1101
L41
FCM2012K-121T 0805
DVOC_D11
R304
10K_R
TZ1130
Z1118
Z1110
Z1125
TZ1121
DVOC_D6
TZ1126
+
CT43
10u/10V_1206
CA210
0.1u_X7R
CA201
0.1u_X7R
CA198
0.1u_X7R
U1-
12
TZ1114
R323
10K_R
LCDPWR
12
TZ1112
R298
330_R
CA197
0.1u_X7R
L0-
12
XI/FIN
DVOC_D3
Z1128
Z1123
+3V
TZ1127
R303
1K
+
CT44
10u/10V_1206
DVOC_D1
R327
330
C220
10p_R
DVOC_D7
R593
0_R
DVOC_D8
Z1122
TZ1104
Z1106
C219
18p
PCIRST#1
15,21,22
LIGHTPWR
12
+3V
Z1133
Z1115
DVOC_FLDSTL
7
L3-
12
R329
0_R
DVOC_CLK
7
+1.5V
R318
0_R
Z1124
Z1135
CA203
0.1u_X7R
+3V
Z1117
C222
18p
U3-
12
CH7017A-CLK
4
XI/FIN
R315
2.4K_1%
CA205
0.1u_X7R
DVOC_D[0..11]
MI2C_DATA
CA191
0.1u_X7R
CA195
0.1u_X7R
U2+
12
Z1126
Z1116
TZ1107
Z1127
TZ1108
Z1130
TZ1119
Z1107
R319
10K
Z1111
MI2C_CLK
R325
10K
R322
10K_R
U1+
12
L2+
12
MI2C_DATA
R331
0_R
L42
FCM2012K-121T 0805
+
CT47
10u/10V_1206
U3+
12
TZ1132
DVOC_D0
+
CT51
10u/10V_1206
DVOC_D5
Z1132
TZ1128
UCLK-
12
+5V
L40
FCM2012K-121T 0805
Z1134
CA211
0.1u_X7R
+
CT50
10u/10V_1206
TZ1109
R297
330_R
CA200
0.1u_X7R
MI2C_CLK
7
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