VCC-5CL5M/R
Rev.905-0073-01
©2017 CIS Corporation. All rights reserved.
9
3.4.
Output Data Configuration
Port Allocation
Output Data Array
P_A7
P_A6
P_C6
P_B7
P_B6
LVAL
P_C5
X3_OUT3
X2_OUT2
DVAL
EEN
P_C7
FVAL
P_C2
X1_OUT1
P_C1
P_C0
P_B5
P_B4
P_B3
P_B2
P_C4
P_C3
CLK_OUT
P_A0
P_B1
X0_OUT0
P_B0
P_A5
P_A2
P_A1
P_A4
P_A3
Port
8bit Output 1
~
3Tap
10bit Output 1
~
2Tap
12bit Output 1
~
2Tap
Port A0
DA[0] LSB
DA[0] LSB
DA[0] LSB
Port A1
DA[1]
DA[1]
DA[1]
Port A2
DA[2]
DA[2]
DA[2]
Port A3
DA[3]
DA[3]
DA[3]
Port A4
DA[4]
DA[4]
DA[4]
Port A5
DA[5]
DA[5]
DA[5]
Port A6
DA[6]
DA[6]
DA[6]
Port A7
DA[7] MSB
DA[7]
DA[7]
Port B0
DB[0] LSB
DA[8]
DA[8]
Port B1
DB[1]
DA[9] MSB
DA[9] MSB
Port B2
DB[2]
DA[10]
Port B3
DB[3]
DA[11]
Port B4
DB[4]
DB[8]
DB[8]
Port B5
DB[5]
DB[9] MSB
DB[9]
Port B6
DB[6]
DB[10]
Port B7
DB[7] MSB
DB[11] MSB
Port C0
DC[0] LSB
DB[0] LSB
DB[0] LSB
Port C1
DC[1]
DB[1]
DB[1]
Port C2
DC[2]
DB[2]
DB[2]
Port C3
DC[3]
DB[3]
DB[3]
Port C4
DC[4]
DB[4]
DB[4]
Port C5
DC[5]
DB[5]
DB[5]
Port C6
DC[6]
DB[6]
DB[6]
Port C7
DC[7] MSB
DB[7]
DB[7]