CS5460A
34
DS284PP4
Step H3 - Clear the Status Register by writing
back the value read in step H0.
Step H4 - Re-enable interrupts.
Step H5 - Return from interrupt service routine.
This handshaking procedure insures that any
new interrupts activated between steps H0 and
H3 are not lost (cleared) by step H3.
4.4.1.3 INT Active State
The behavior of the INT pin is controlled by the SI1
and SI0 bits of the Configuration Register. The pin
can be active low (default), active high, active on a
return to logic 0 (pulse-low), or active on a return
to logic 1 (pulse-high).
If the interrupt output signal format is set for either
active-high or active-low assertion, the interrupt
condition is cleared when the bits of the Status
Register are returned to their inactive state. If the
interrupt output signal format is set for either
pulse-high or pulse-low, note that the duration of
the INT pulse will be at least one MCLK/K cycle,
although in some cases the pulse may last for 2
MCLK/K cycles.
4.4.1.4 Exceptions
The IC (Invalid Command) bit of the Status Regis-
ter can only be cleared by performing the port ini-
tialization sequence. This is also the only Status
Register bit that is active low.
To properly clear the WDT (Watch Dog Timer) bit
of the Status Register, first read the Energy Regis-
ter, then clear the bit in the Status Register.
4.4.2 Watch Dog Timer
The Watch Dog Timer (WDT) is provided as a
means of alerting the system that there is a potential
breakdown in communication with the microcon-
troller. By allowing the WDT to cause an interrupt,
a controller can be brought back, from some un-
known code space, into the proper code for pro-
cessing the data created by the converter. The
time-out is preprogrammed to approximately 5 sec-
onds. The countdown restarts each time the Energy
Register is read. Under typical situations, the Ener-
gy Register is read every second. As a result, the
WDT will not time out. Other applications that use
the watchdog timer will need to ensure that the En-
ergy Register is read at least once in every 5 second
span.
4.5 Oscillator Characteristics
XIN and XOUT are the input and output, respec-
tively, of an inverting amplifier to provide oscilla-
tion and can be configured as an on-chip oscillator,
as shown in Figure 16. The oscillator circuit is de-
signed to work with a quartz crystal or a ceramic
resonator. To reduce circuit cost, two load capaci-
tors C1 are integrated in the device, one between
XIN and DGND, one between XOUT and DGND.
Lead lengths should be minimized to reduce stray
capacitance. With these load capacitors, the oscil-
lator circuit is capable of oscillation up to 20 MHz,
if +5V is used for VD+. Note that for VD+ =
+3.3V, the maximum crystal frequency that can be
used is 5 MHz.
To drive the device from an external clock source,
XOUT should be left unconnected while XIN is
driven by the external circuitry. There is an ampli-
fier between XIN and the digital section which pro-
vides CMOS level signals. This amplifier works
with sinusoidal inputs so there are no problems
with slow edge times.
The CS5460A can be driven by a clock ranging
from 2.5 to 20 MHz. The user must appropriately
set the K divider value such that MCLK/K will be
some value between 2.5 MHz and 5 MHz. The K
divider value is set with the K[3:0] bits in the Con-
figuration Register.
As an example, if XIN =
MCLK = 15 MHz, and K is set to 5, then MCLK/K
= 3 MHz, which is a valid value for MCLK/K.
Note that if the K[3:0] bits are all set to zero, the
value of the K divider value is 16.
Summary of Contents for CS5460A
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