Cirrus Logic CS5460A, Manual

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CS5460A
24 DS284PP4
During the read cycle, the SYNC0 command
(NOP) should be strobed on the SDI port while
clocking the data from the SDO port.
3.4 System Initialization
A software or hardware reset can be initiated at any
time. The software reset is initiated by writing a
logic 1 to the RS (Reset System) bit in the Config-
uration Register, which automatically returns to
logic 0 after reset. At the end of the 32
nd
SCLK
(i.e., 8 bit command word and 24 bit data word) in-
ternal synchronization delays the loading of the
Configuration Register by 3 or 4 DCLK cycles.
Then the reset circuit initiates the reset routine on
the 1
st
falling edge of MCLK.
A hardware reset is initiated when the RESET pin
is forced low for at least 50 ns. The RESET signal
is asynchronous, requiring no MCLKs for the part
to detect and store a reset event. The RESET pin is
a Schmitt Trigger input, which allows it to accept
slow rise times and/or noisy control signals. (It is
not uncommon to experience temporary periods of
abnormally high noise and/or slow, gradual resto-
ration of power, during/after a power “black-out”
or power “brown-out” event.) Once the RESET
pin is de-asserted, the internal reset circuitry re-
mains active for 5 MCLK cycles to insure resetting
the synchronous circuitry in the device. The modu-
lators are held in reset for 12 MCLK cycles after
RESET is de-asserted. After a hardware or software
reset, the internal registers (some of which may
drive output pins) will be reset to their default values
on the first MCLK received after detecting a reset
event (see Table 3). The CS5460A will then assume
its active state. (The term active state, as well as the
other possible power states of the CS5460A, are de-
scribed in Section 3.6).
The reader should refer to Section 5 for a complete
description of the registers listed in Table 3.
3.5 Serial Port Initialization
It is possible for the serial interface to become un-
synchronized with respect to the SCLK input. If
this occurs, any attempt to clock valid CS5460A
commands into the serial interface will result in ei-
ther no operation or unexpected operation because
the CS5460A will not interpret the input command
bits correctly. The CS5460A’s serial port must then
be re-initialized. To initialize the serial port, any of
the following actions can be performed:
1) Power on the CS5460A. (Or if the device is al-
ready powered on, recycle the power.)
2) Hardware Reset.
3) Issue the Serial Port Initialization Sequence,
which is performed by clocking 3 (or more)
SYNC1 command bytes (0xFF) followed by
one SYNC0 command byte (0xFE) to the serial
interface.
Configuration Register: 0x000001
DC offset registers: 0x000000
Gain registers 0x400000
Pulse-Rate Register: 0x0FA000
Cycle-Counter Register: 0x000FA0
Timebase Register: 0x800000
Status Register: (see Section 5)
Mask Register: 0x000000
Control Register: 0x000000
AC offset registers: 0x000000
Power Offset Register: 0x000000
All data registers: 0x000000
All unsigned data registers 0x000000
Table 3. Default Register Values upon Reset Event